View 7782_307648.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

M58CR032C M58CR032D
32 Mbit (2Mb x 16, Dual Bank, Burst ) 1.8V Supply Flash Memory
PRELIMINARY DATA
FEATURES SUMMARY s SUPPLY VOLTAGE - VDD = 1.65V to 2V for Program, Erase and Read - VDDQ = 1.65V to 3.3V for I/O Buffers
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Figure 1. Packages
- VPP = 12V for fast Program (optional) SYNCHRONOUS / ASYNCHRONOUS READ - Burst mode Read: 54MHz - Page mode Read (4 Words Page) - Random Access: 85, 100, 120 ns
FBGA
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PROGRAMMING TIME - 10s by Word typical - Double/Quadruple Word programming option
TFBGA56 (ZB) 6.5 x 10 mm
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MEMORY BLOCKS - Dual Bank Memory Array: 8/24 Mbit - Parameter Blocks (Top or Bottom location)
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DUAL OPERATIONS - Read in one Bank while Program or Erase in other - No delay between Read and Write operations
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ELECTRONIC SIGNATURE - Manufacturer Code: 20h - Top Device Code, M58CR032C: 88C8h - Bottom Device Code, M58CR032D: 88C9h
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BLOCK LOCKING - All blocks locked at Power up - Any combination of blocks can be locked - WP for Block Lock-Down
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SECURITY - 64 bit user programmable OTP cells - 64 bit unique device identifier - One parameter block permanently lockable
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COMMON FLASH INTERFACE (CFI) 100,000 PROGRAM/ERASE CYCLES per BLOCK
September 2002
This is preliminary information on a new product now in development or undergoing evaluation. Details are subject to change without notice.
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TABLE OF CONTENTS SUMMARY DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Figure 2. Logic Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Table 1. Signal Names . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Figure 3. TFBGA Connections (Top view through package) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Table 2. Bank Architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Figure 4. Memory Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Figure 5. Security Block and Protection Register Memory Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 SIGNAL DESCRIPTIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Address Inputs (A0-A20). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Data Inputs/Outputs (DQ0-DQ15). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Chip Enable (E). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Output Enable (G). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Write Enable (W). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Write Protect (WP). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Reset/Power-Down (RP). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Latch Enable (L). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Clock (K).. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Wait (WAIT). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 VDD Supply Voltage (1.65V to 2V). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 VDDQ Supply Voltage (1.65V to 3.3V). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 VPP Program Supply Voltage (12V). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 VSS and V SSQ Grounds. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 BUS OPERATIONS. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 Asynchronous Read. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 Asynchronous Page Read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 Asynchronous Write. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 Output Disable. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 Standby. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 Reset/Power-Down.. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 Automatic Standby. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 Synchronous Single Read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 Synchronous Burst Read. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Table 3. Bus Operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Figure 6. Synchronous Single Read Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Burst Configuration Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Read Select Bit (M15) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 X-Latency Bits (M13-M11). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Power-Down Bit (M10). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Wait Bit (M8). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Burst Type Bit (M7).. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Valid Clock Edge Bit (M6).. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
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Wrap Burst Bit (M3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Burst length Bits (M2-M0).. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Table 4. Burst Configuration Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Table 5. Burst Type Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 Figure 7. X-Latency Configuration Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 Figure 8. Wait Configuration Sequence. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 COMMAND INTERFACE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 Read Command. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 Read Status Register Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 Read Electronic Signature Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 Read CFI Query Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 Clear Status Register Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 Block Erase Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 Bank Erase Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 Program Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 Double Word Program Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 Quadruple Word Program Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 Program/Erase Suspend Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 Program/Erase Resume Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 Protection Register Program Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 Block Lock Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 Block Unlock Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 Block Lock-Down Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 Set Burst Configuration Register Command. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 Table 6. Commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 Table 7. Dual Bank Operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 Table 8. Read Electronic Signature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 Table 9. Read Block Protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 Table 10. Read Protection Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 Table 11. Identifier Codes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 Table 12. Program, Erase Times and Program, Erase Endurance Cycles . . . . . . . . . . . . . . . . . . . 26 BLOCK LOCKING. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 Reading a Block's Lock Status . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 Locked State . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 Unlocked State . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 Lock-Down State . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 Locking Operations During Erase Suspend . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 Block Lock Status . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 Lock Status . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 STATUS REGISTER . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 Program/Erase Controller Status (Bit 7) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 Erase Suspend Status (Bit 6) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 Erase Status (Bit 5) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
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Program Status (Bit 4) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 VPP Status (Bit 3). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 Program Suspend Status (Bit 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 Block Protection Status (Bit 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 Reserved (Bit 0). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 Table 15. Status Register Bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 MAXIMUM RATING. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 Table 16. Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 DC AND AC PARAMETERS. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 Table 17. Operating and AC Measurement Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 Figure 9. AC Measurement I/O Waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 Figure 10. AC Measurement Load Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 Table 18. Capacitance. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 Table 19. DC Characteristics - Currents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 Table 20. DC Characteristics - Voltages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 Figure 11. Asynchronous Read AC Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 Figure 12. Asynchronous Page Read AC Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 Table 21. Asynchronous Read AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 Figure 13. Synchronous Burst Read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 Table 22. Synchronous Burst Read AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 Figure 14. Write AC Waveforms, Write Enable Controlled . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 Table 23. Write AC Characteristics, Write Enable Controlled . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 Figure 15. Write AC Waveforms, Chip Enable Controlled . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 Table 24. Write AC Characteristics, Chip Enable Controlled . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 Figure 16. Reset and Power-up AC Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 Table 25. Reset and Power-up AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 PACKAGE MECHANICAL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 Figure 17. TFBGA56 6.5x10mm - 8x7 ball array, 0.75 mm pitch, Bottom View Package Outline. . 45 Table 26. TFBGA56 6.5x10mm - 8x7 ball array, 0.75 mm pitch, Package Mechanical Data . . . . . 45 PART NUMBERING . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 Table 27. Ordering Information Scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 REVISION HISTORY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 Table 28. Document Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 APPENDIX A. COMMON FLASH INTERFACE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 Table 29. Query Structure Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 Table 30. CFI Query Identification String . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 Table 31. CFI Query System Interface Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 Table 32. Device Geometry Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 Table 33. Primary Algorithm-Specific Extended Query Table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
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Table 34. Burst Read Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 Table 35. Security Code Area . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 APPENDIX B. FLOWCHARTS AND PSEUDO CODES. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 Figure 18. Program Flowchart and Pseudo Code . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 Figure 19. Double Word Program Flowchart and Pseudo code . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 Figure 20. Quadruple Word Program Flowchart and Pseudo Code . . . . . . . . . . . . . . . . . . . . . . . . 55 Figure 21. Program Suspend & Resume Flowchart and Pseudo Code . . . . . . . . . . . . . . . . . . . . . 56 Figure 22. Block Erase Flowchart and Pseudo Code . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57 Figure 23. Erase Suspend & Resume Flowchart and Pseudo Code. . . . . . . . . . . . . . . . . . . . . . . . 58 Figure 24. Locking Operations Flowchart and Pseudo Code . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59 Figure 25. Protection Register Program Flowchart and Pseudo Code . . . . . . . . . . . . . . . . . . . . . . 60 APPENDIX C. COMMAND INTERFACE STATE TABLES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61 Table 36. Command Interface States - Lock table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61 Table 37. Command Interface States - Modify Table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62
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M58CR032C, M58CR032D
SUMMARY DESCRIPTION The M58CR032 is a 32 Mbit (2Mbit x16) non-volatile Flash memory that may be erased electrically at block level and programmed in-system on a Word-by-Word basis using a 1.65V to 2.0V V DD supply for the circuitry and a 1.65V to 3.3V V DDQ supply for the Input/Output pins. An optional 12V VPP power supply is provided to speed up customer programming. The VPP pin can also be used as a control pin to provide absolute protection against program or erase. The device features an asymmetrical block architecture. M58CR032 has an array of 71 blocks and is divided into two banks, Banks A and B, providing Dual Bank operations. While programming or erasing in Bank A, read operations are possible in Bank B or vice versa. Only one bank at a time is allowed to be in program or erase mode. It is possible to perform burst reads that cross bank boundaries. The bank architecture is summarized in Table 2, and the memory maps are shown in Figure 4. The Parameter Blocks are located at the top of the memory address space for the M58CR032C and at the bottom for the M58CR032D. Each block can be erased separately. Erase can be suspended, in order to perform either read or program in any other block, and then resumed. Program can be suspended to read data in any other block and then resumed. Each block can be programmed and erased over 100,000 cycles. Program and Erase commands are written to the Command Interface of the memory. An on-chip Program/Erase Controller takes care of the timings necessary for program and erase operations. The end of a program or erase operation can be detected and any error conditions identified in the
Status Register. The command set required to control the memory is consistent with JEDEC standards. The device supports synchronous burst read and asynchronous read from all blocks of the memory array; at power-up the device is configured for page mode read. In synchronous burst mode, data is output on each clock cycle at frequencies of up to 54MHz. The M58CR032 features an instant, individual block locking scheme that allows any block to be locked or unlocked with no latency, enabling instant code and data protection. All blocks have three levels of protection. They can be locked and locked-down individually preventing any accidental programming or erasure. There is an additional hardware protection against program and erase. When V PP VPPLK all blocks are protected against program or erase. All blocks are locked at Power Up. The device includes a 128 bit Protection Register and a Security Block to increase the protection of a system's design. The Protection Register is divided into two 64 bit segments. The first segment contains a unique device number written by ST, while the second one is one-time-programmable by the user. The user programmable segment can be permanently protected. The Security Block, parameter block 0, can be permanently protected by the user. Figure 5, shows the Security Block and Protection Register Memory Map. The memory is offered in a TFBGA56, 0.75 mm ball pitch package and is supplied with all the bits erased (set to '1').
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Figure 2. Logic Diagram Table 1. Signal Names
A0-A20 Address Inputs Data Input/Outputs or Address Inputs, Command Inputs Chip Enable Output Enable Write Enable Reset/Power-down Write Protect Burst Clock Latch Enable Wait Data in Burst Mode Supply Voltage Supply Voltage for Input/Output Buffers Optional Supply Voltage for Fast Program & Erase Ground Ground Input/Output Supply Not Connected Internally
VDD VDDQ VPP 21 A0-A20 W E G RP WP L K M58CR032C M58CR032D WAIT 16 DQ0-DQ15
DQ0-DQ15 E G W RP WP K L WAIT VDD VDDQ
VSS
AI90067
VPP VSS VSSQ NC
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Figure 3. TFBGA Connections (Top view through package)
1 2 3 4 5 6 7 8
A
A11
A8
VSS
VDD
VPP
A18
A6
A4
B
A12
A9
A20
K
RP
A17
A5
A3
C
A13
A10
NC
L
W
A19
A7
A2
D
A15
A14
WAIT
A16
DQ12
WP
NC
A1
E
VDDQ
DQ15
DQ6
DQ4
DQ2
DQ1
E
A0
F
VSS
DQ14
DQ13
DQ11
DQ10
DQ9
DQ0
G
G
DQ7
VSSQ
DQ5
VDD
DQ3
VDDQ
DQ8
VSSQ
AI90001
Table 2. Bank Architecture
Bank Size Bank A Bank B 8 Mbit 24 Mbit Parameter Blocks 8 blocks of 4 KWord Main Blocks 15 blocks of 32 KWord 48 blocks of 32 KWord
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Figure 4. Memory Map
Top Boot Block Address lines A20-A0 000000h 007FFFh Bank B 512 Kbit or 32 KWord Total of 48 Main Blocks 000000h 000FFFh Bottom Boot Block Address lines A20-A0 64 Kbit or 4 KWord Total of 8 Parameter Blocks 007000h Bank A 512 Kbit or 32 KWord Total of 15 Main Blocks 007FFFh 008000h 00FFFFh 64 Kbit or 4 KWord 512 Kbit or 32 KWord Total of 15 Main Blocks
178000h 17FFFFh 180000h 187FFFh
512 Kbit or 32 KWord
1F0000h Bank A 1F7FFFh 1F8000h 1F8FFFh
512 Kbit or 32 KWord 64 Kbit or 4 KWord Total of 8 Parameter Blocks
078000h 07FFFFh 080000h 087FFFh Bank B
512 Kbit or 32 KWord 512 Kbit or 32 KWord Total of 48 Main Blocks
1FF000h 1FFFFFh
64 Kbit or 4 KWord
1F8000h 1FFFFFh
512 Kbit or 32 KWord
AI90069
Figure 5. Security Block and Protection Register Memory Map
PROTECTION REGISTER 88h SECURITY BLOCK 85h 84h Parameter Block # 0 81h 80h Protection Register Lock 2 1 0 Unique device number User Programmable OTP
AI90004
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SIGNAL DESCRIPTIONS See Figure 2 Logic Diagram, and Table 1, Signal Names, for a brief overview of the signals connected to this device. Address Inputs (A0-A20). The Address Inputs select the cells in the memory array to access during Bus Read operations. During Bus Write operations they control the commands sent to the Command Interface of the internal state machine. The address inputs for the memory array are latched on the rising edge of Latch Enable L. The address latch is transparent when L is at VIL. In synchronous operations the address is also latched on the first rising/falling edge of K (depending on clock configuration) when L is low. During a Write operation the address is latched on the rising edge of L or W, whichever occurs first. Data Inputs/Outputs (DQ0-DQ15). The Data Inputs/Outputs output the data stored at the selected address during a Bus Read operation. During Bus Write operations they represent the commands sent to the Command Interface of the internal state machine. Both input data and commands are latched on the rising edge of Write Enable, W. When Chip Enable, E, and Output Enable, G, are at V IL the data bus outputs data from the Memory Array, the Electronic Signature, Manufacturer or Device codes, the Block Protection Status, the Burst Configuration Register, the Protection Register or the Status Register. The data bus is high impedance when the chip is deselected, Output Enable, G, is at VIH, or Reset/Power-Down, RP, is at VIL. Chip Enable (E). The Chip Enable input activates the memory control logic, input buffers, decoders and sense amplifiers. When Chip Enable, E, is at VIH, the memory is deselected and the power consumption is reduced to the standby level. Chip Enable can also be used to control writing to the Command Interface and to the memory array, while Write Enable, W, remains at VIL. Output Enable (G). The Output Enable gates the outputs through the data buffers during a read operation. When Output Enable, G, is at VIH the outputs are high impedance. Write Enable (W). The Write Enable controls the Bus Write operation of the memory's Command Interface. Data are latched on the rising edge of Write Enable. Write Protect (WP). Write Protect is an input that gives an additional hardware protection for each block. When Write Protect is at V IL, the Lock-Down is enabled and the protection status of the block cannot be changed. When Write Protect is at VIH, the Lock-Down is disabled and the block can be locked or unlocked. (refer to Table 10, Read Protection Register).
Reset/PowerReset/Power-Down (RP). The Down input provides hardware reset of the memory, and/or Power-Down functions, depending on the Burst Configuration Register status. A Reset or Power-Down of the memory is achieved by pulling RP to VIL for at least tPLPH. When the reset pulse is given, the memory will recover from PowerDown (when enabled) in a minimum of tPHEL, tPHLL or tPHWL (see Table 25 and Figure 16) after the rising edge of RP. After a Reset or Power-Up the device is configured for asynchronous page read (M15=1) and the power save function is disabled (M10=0). All blocks are locked after a Reset or Power-Down. Either Chip Enable or Write Enable must be tied to VIH during Power-Up to allow maximum security and the possibility to write a command on the first rising edge of Write Enable. Latch Enable (L). Latch Enable latches the address bits A0-A20 on its rising edge. The address latch is transparent when L is at V IL and it is inhibited when L is at V IH . Clock (K). The clock input synchronizes the memory to the microcontroller during burst mode read operation; the address is latched on a K edge (rising or falling, according to the configuration settings) when L is at VIL. K is don't care during asynchronous page mode read and in write operations. Wait (WAIT). Wait is an output signal used during burst mode read, indicating whether the data on the output bus are valid or a wait state must be inserted. This output is high impedance when Chip Enable or Output Enable are at VIH or Reset/Power-Down is at VIL. It can be configured to be active during the wait cycle or one clock cycle in advance. proVDD Supply Voltage (1.65V to 2V). VDD vides the power supply to the internal core of the memory device. It is the main power supply for all operations (Read, Program and Erase). It ranges from 1.65V to 2.0V. VDDQ Supply Voltage (1.65V to 3.3V). VDDQ provides the power supply to the I/O pins and enables all Outputs to be powered independently from V DD. VDDQ can be tied to VDD or it can use a separate supply. It can be powered either from 1.65V to 2.0V or from 1.65V to 3.3V. VPP Program Supply Voltage (12V). VPP is a power supply pin. The Supply Voltage VDD and the Program Supply Voltage VPP can be applied in any order. The pin can also be used as a control input. The two functions are selected by the voltage range applied to the pin. If VPP is kept in a low voltage range (0V to 2V) V PP is seen as a control input. In this case a voltage lower than VPPLK gives an absolute protection against program or erase,
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while VPP > VPP1 enables these functions (see Table 19, DC Characteristics for the relevant values). VPP is only sampled at the beginning of a program or erase; a change in its value after the operation has started does not have any effect on Program or Erase, however for Double or Quadruple Word Program the results are uncertain. If V PP is in the range 11.4V to 12.6V it acts as a power supply pin. In this condition V PP must be stable until the Program/Erase algorithm is completed (see Table 16 and 17). In read mode the current sunk is less then 0.5mA, while during program and erase operations the current may increase up to 10mA. VSS and VSSQ Grounds. VSS and V SSQ grounds are the reference for the core supply and the input/ output voltage measurements respectively. Note: Each device in a system should have VDD, VDDQ and V PP decoupled with a 0.1F capacitor close to the pin. See Figure 10, AC Measurement Load Circuit. The PCB trace widths should be sufficient to carry the required VPP program and erase currents.
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M58CR032C, M58CR032D
BUS OPERATIONS There are two types of bus operations that control the device: Asynchronous (Read, Page Read, Write, Output Disable, Standby, Automatic Standby and Reset/Power-Down) and Synchronous (Synchronous Read and Synchronous Burst Read). The Dual Bank architecture of the M58CR032 allows read/write operations in Bank A, while read operations are being executed in Bank B or vice versa. Write operations are only allowed in one bank at a time (see Table 7). See Table 3, Bus Operations, for a summary. Typically glitches of less than 5ns on Chip Enable or Write Enable are ignored by the memory and do not affect bus operations. Asynchronous Read. Asynchronous Read operations read from the Memory Array, or specific registers (Electronic Signature, Status Register, CFI, Block Protection Status, Read Configuration Register status and Protection Register) in the Command Interface. A valid Asynchronous Bus Read operation involves setting the desired address on the Address Inputs, applying a Low signal, V IL, to Chip Enable and Output Enable and keeping Write Enable High, VIH. The address is latched on the rising edge of the Latch, L, input. The Data Inputs/Outputs will output the value, see Figure 11, Asynchronous Read AC Waveforms, and Table 21, Asynchronous Read AC Characteristics, for details of when the output becomes valid. According to the device configuration the following Read operations: Electronic Signature, Status Register, CFI, Block Protection Status, Burst Configuration Register Status and Protection Register must be accessed as asynchronous read or as single synchronous read. Asynchronous Page Read. Asynchronous Page Read operations can be used to read the content of the memory array, where data is internally read and stored in a page buffer. The page has a size of 4 words and is addressed by A0 and A1 address inputs. Valid bus operations are the same as Asynchronous Bus Read operations but with different timings. The first read operation within the page has identical timings, subsequent reads within the same page have much shorter access times. If the page changes then the normal, longer timings apply again. See Figure 12, Asynchronous Page Read AC Waveforms and Table 21, Asynchronous Read AC Characteristics for details on when the outputs become valid. Asynchronous Page Read is the default state of the device when exiting power-down or after power-up.
Asynchronous Write. Bus Write operations are used to write to the Command Interface of the memory or latch Input Data to be programmed. A valid Bus Write operation begins by setting the desired address on the Address Inputs and setting Chip Enable, E, and Write Enable, W, to V IL and Output Enable to VIH. Addresses are latched on the rising edge of L, W or E whichever occur first. Commands and Input Data are latched on the rising edge of W or E whichever occurs first. Output Enable must remain High, V IH, during the whole Bus Write operation. See Figures 14 and 15, Write AC Waveforms, and Tables 23 and 24, Write AC Characteristics, for details of the timing requirements. Write operations are asynchronous and the clock is ignored during write. Output Disable. The data outputs are high impedance when the Output Enable, G, and Write Enable, W, are High, V IH. Standby. When Chip Enable is High, VIH, and the Program/Erase Controller is idle, the memory enters Standby mode and the Data Inputs/Outputs pins are placed in the high impedance state, independent of Output Enable, G, or Write Enable, W. For the Standby current level see Table 19, DC Characteristics. Reset/Power-Down. The memory is in PowerDown when the Burst Configuration Register is set for Power-Down and RP is at VIL. The power consumption is reduced to the Power-Down level, and Outputs are in high impedance, independent of Chip Enable E, Output Enable G or Write Enable W. The memory is in reset mode when the Burst Configuration Register is set for Reset and RP is at VIL. The power consumption is the same of the standby and the outputs are in high impedance. After a Reset/Power-Down the device defaults to Asynchronous Page Read, the Status Register is cleared and the Burst configuration register defaults to Asynchronous Page read. Automatic Standby. If CMOS levels (V DD 0.2V) are used to drive the bus and the bus is inactive for 150ns or more in Read mode, the memory enters Automatic Standby where the internal Supply Current is reduced to the Standby Supply Current, IDD2. The Data Inputs/Outputs will still output data if a Bus Read operation is in progress. The automatic standby feature is not available when the device is configured for synchronous burst mode. Synchronous Single Read. Synchronous single Reads can be used to read the Electronic Signature, Status Register, CFI, Block Protection Status, Burst Configuration Register Status or
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M58CR032C, M58CR032D
Protection Register, see Figure 6, for an example of a single synchronous read operation. Synchronous Burst Read. The device also supports a synchronous burst read. In this mode a burst sequence is started at the first clock edge (rising or falling according to configuration settings) after the falling edge of Latch Enable. After a configurable delay of 2 to 5 clock cycles a new data is output at each clock cycle. The burst sequence may be configured to be sequential or interleaved and for a length of 4 or 8 words or for continuous burst mode (see Table 5, Burst Type Definition). Wrap and no-wrap modes are also supported. A WAIT signal may be asserted to indicate to the system that an output delay will occur. This delay will depend on the starting address of the burst sequence; the worst case delay will occur when the sequence is crossing a 64 word boundary and the starting address was at the end of a four word boundary. See the Burst Configuration Register command for more details on all the possible settings for the synchronous burst read (see Table 4). It is possible to perform burst read across bank boundaries (all banks in read array mode).
Table 3. Bus Operations
Operation Asynchronous Read Asynchronous Page Read Asynchronous Write Output Disable Standby Reset / Power-Down Synchronous Read Synchronous Burst Read E VIL VIL VIL VIL VIH X VIL VIL G VIL VIL VIH VIH X X VIL VIL W VIH VIH VIL VIH X X VIH VIH L VIL(3) VIL(3) VIL(3) X X X T(2) T(2) K X X X X X X T(2) T(2) RP VIH VIH VIH VIH VIH VIL VIH VIH WP X X VIH VIH X X X X DQ15-DQ0 Data Output Data Output Data Input Hi-Z Hi-Z Hi-Z Data Output Data Output
Note: 1. X = Don't care. 2. T = transition, falling edge for L, rising or falling edge for K depending on M6 in the Burst Configuration Register. The burst sequence is started on the first active clock edge after the falling edge of Latch Enable. 3. L can be tied to VIH if the valid address has been previously latched
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M58CR032C, M58CR032D
Figure 6. Synchronous Single Read Operation
K
L
A20-A0
VALID ADDRESS X latency = 2
DQ15-DQ0 X latency = 3 DQ15-DQ0 X latency = 4 DQ15-DQ0
VALID DATA
NOT VALID
NOT VALID
NOT VALID
VALID DATA
NOT VALID
NOT VALID
VALID DATA
NOT VALID
AI90103
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M58CR032C, M58CR032D
Burst Configuration Register The Burst Configuration Register is used to configure the type of bus access that the memory will perform. The Burst Configuration Register is set through the Command Interface. After a Reset or PowerUp the device is configured for asynchronous page read (M15 = 1) and the power save function is disabled (M10 = 0). The Burst Configuration Register bits are described in Table 4. They specify the selection of the burst length, burst type, burst X latency and the Read operation. Refer to Figures 7 and 8 for examples of synchronous burst configurations. Read Select Bit (M15). The Read Select bit, M15, is used to switch between asynchronous and synchronous Bus Read operations. When the Read Select bit is set to '1', Bus Read operations are asynchronous; when the Read Select but is set to '0', Bus Read operations are synchronous. Synchronous Burst Read is supported in both parameter and main blocks and can be performed across banks. On reset or power-up the Read Select bit is set to'1' for asynchronous access. X-Latency Bits (M13-M11). The X-Latency bits are used during Synchronous Bus Read operations to set the number of clock cycles between the address being latched and the first data becoming available. For correct operation the X-Latency bits can only assume the values in Table 4, Burst Configuration Register. The correspondence between X-Latency settings and the maximum sustainable frequency must be calculated taking into account some system parameters. Two conditions must be satisfied: - (n + 1) tK tACC - tAVK_CPU + tQVK_CPU - tK > tKQV + tQVK_CPU where "n" is the chosen X-Latency configuration code, t K is the clock period, tAVK_CPU is Clock to Address Valid, L Low or E Low, whichever occurs last, and tQVK_CPU is the data setup time required by the system CPU. Power-Down Bit (M10). The Power-Down bit is used to enable or disable the power-down function. When the Power-Down bit is set to `0' (default) the power-down function is disabled. When the Power-Down bit is set to `1' power-down is enabled and the device goes into the power-down state where the I DD supply current is reduced to a typical figure of I DD2. if this function is disabled the Reset/Power-Down, RP, pin causes only a reset of the device and the supply current is the standby value. The recovery time after a Reset/Power-Down, RP, pulse is significantly longer when power-down is enabled (see Table 25). Wait Bit (M8). In burst mode the Wait bit controls the timing of the Wait output pin, WAIT. When the Wait bit is '0' the Wait output pin is asserted during the wait state. When the Wait bit is '1' (default) the Wait output pin is asserted one clock cycle before the wait state. WAIT is asserted during a continuous burst and also during a 4 or 8 burst length if no-wrap configuration is selected. WAIT is not asserted during asynchronous reads, single synchronous reads or during latency in synchronous reads. Burst Type Bit (M7). The Burst Type bit is used to configure the sequence of addresses read as sequential or interleaved. When the Burst Type bit is '0' the memory outputs from interleaved addresses; when the Burst Type bit is '1' (default) the memory outputs from sequential addresses. See Tables 5, Burst Type Definition, for the sequence of addresses output from a given starting address in each mode. Valid Clock Edge Bit (M6). The Valid Clock Edge bit, M6, is used to configure the active edge of the Clock, K, during Synchronous Burst Read operations. When the Valid Clock Edge bit is '0' the falling edge of the Clock is the active edge; when the Valid Clock Edge bit is '1' the rising edge of the Clock is active. Wrap Burst Bit (M3). The burst reads can be confined inside the 4 or 8 Double-Word boundary (wrap) or overcome the boundary (no wrap). The Wrap Burst bit is used to select between wrap and no wrap. When the Wrap Burst bit is set to `0' the burst read wraps; when it is set to `1' the burst read does not wrap. Burst length Bits (M2-M0). The Burst Length bits set the number of Words to be output during a Synchronous Burst Read operation; 4 words, 8 words or continuous burst, where all the words are read sequentially. In continuous burst mode the burst sequence can cross bank boundaries. In continuous burst mode or in 4, 8 words no-wrap, depending on the starting address, the device activates the WAIT output to indicate that a delay is necessary before the data is output. If the starting address is aligned to a 4 word boundary no wait states are needed and the WAIT output is not activated. If the starting address is shifted by 1,2 or 3 positions from the four word boundary, WAIT will be asserted for 1, 2 or 3 clock cycles when the burst sequence crosses the first 64 word boundary, to indicate that the device needs an internal delay to read the successive words in the array. WAIT will
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M58CR032C, M58CR032D
be asserted only once during a continuous burst access. See also Table 5, Burst Type Definition. Table 4. Burst Configuration Register
Bit M15 M14 010 011 M13-M11 X-Latency (2) 100 101 111 Description 0 Read Select 1 Asynchronous Page Read (Default at power-on) Reserved 2 clock latency 3 clock latency 4 clock latency 5 clock latency Reserved Value Synchronous Burst Read Description
M14, M9, M5 and M4 are reserved for future use.
Other configurations reserved M10 M9 0 M8 Wait 1 0 M7 Burst Type 1 0 M6 M5-M4 0 M3 Wrapping 1 001 M2-M0 Burst Length 010 111 No wrap 4 words 8 words Continuous (M7 must be set to `1') Valid Clock Edge 1 Rising Burst Clock edge Reserved Wrap Sequential (default) Falling Burst Clock edge WAIT is active one data cycle before wait state (default) Interleaved Power-Down (3) 0 1 Power-Down disabled Power-Down enabled Reserved WAIT is active during wait state
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M58CR032C, M58CR032D
Table 5. Burst Type Definition
Mode Start Address 4 Words Sequential 0 1 2 3 ... Wrap 7 ... 60 61 62 63 Sequential 0 1 2 3 ... No-wrap 7 ... 60 61 62 63 60-61-62-63 61-62-63-WAIT-64 62-63-WAITWAIT-64-65 63-WAIT-WAITWAIT-64-65-66 60-61-62-63-64-65-6667 61-62-63-WAIT-64-6566-67-68 62-63-WAIT-WAIT-6465-66-67-68-69 63-WAIT-WAIT-WAIT64-65-66-67-68-69-70 60-61-62-63-64-65-66... 61-62-63-WAIT-64-65-66... 62-63-WAIT-WAIT-64-65-66... 63-WAIT-WAIT-WAIT-64-6566... 7-8-9-10 7-8-9-10-11-12-13-14 7-8-9-10-11-12-13... 0-1-2-3 1-2-3-4 2-3-4-5 3-4-5-6 Interleaved Sequential 0-1-2-3-4-5-6-7 1-2-3-4-5-6-7-8 2-3-4-5-6-7-8-9... 3-4-5-6-7-8-9-10 Interleaved 0-1-2-3-4-5-6... 1-2-3-4-5-6-7... 2-3-4-5-6-7-8... 3-4-5-6-7-8-9... 60-61-62-63-64-65-66... 61-62-63-WAIT-64-65-66... 62-63-WAIT-WAIT-64-65-66... 63-WAIT-WAIT-WAIT-64-6566... 7-4-5-6 7-6-5-4 7-0-1-2-3-4-5-6 7-6-5-4-3-2-1-0 7-8-9-10-11-12-13... 0-1-2-3 1-2-3-0 2-3-0-1 3-0-1-2 Interleaved 0-1-2-3 1-0-3-2 2-3-0-1 3-2-1-0 8 Words Continuous Burst Sequential 0-1-2-3-4-5-6-7 1-2-3-4-5-6-7-0 2-3-4-5-6-7-0-1 3-4-5-6-7-0-1-2 Interleaved 0-1-2-3-4-5-6-7 1-0-3-2-5-4-7-6 2-3-0-1-6-7-4-5 3-2-1-0-7-6-5-4 0-1-2-3-4-5-6... 1-2-3-4-5-6-7... 2-3-4-5-6-7-8... 3-4-5-6-7-8-9...
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Figure 7. X-Latency Configuration Sequence
K
L
A20-A0
VALID ADDRESS X latency = 2
DQ15-DQ0 X latency = 3 DQ15-DQ0
VALID DATA VALID DATA VALID DATA VALID DATA
VALID DATA VALID DATA VALID DATA X latency = 4
DQ15-DQ0
VALID DATA VALID DATA
AI90105
Figure 8. Wait Configuration Sequence
K
L
E
G
A20-A0
VALID ADDRESS
DQ15-DQ0
VALID DATA VALID DATA
NOT VALID
VALID DATA
WAIT M8 = '0'
WAIT M8 = '1'
AI90106
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COMMAND INTERFACE All Bus Write operations to the memory are interpreted by the Command Interface. Commands consist of one or more sequential Bus Write operations. An internal Program/Erase Controller handles all timings and verifies the correct execution of the Program and Erase commands. The Program/Erase Controller provides a Status Register whose output may be read at any time during, to monitor the progress of the operation, or the Program/Erase states. See Appendix C, Tables 36 and 37, Command Interface States - Lock and Modify Tables, for a summary of the Command Interface. The Command Interface is reset to Read mode when power is first applied, when exiting from Reset or whenever V DD is lower than VLKO . Command sequences must be followed exactly. Any invalid combination of commands will reset the device to Read mode. Refer to Table 6, Commands, in conjunction with the text descriptions below. Read Command. The Read command returns the addressed bank to Read mode. One Bus Write cycle is required to issue the Read command and return the addressed Bank to Read mode. Subsequent read operations will read the addressed location and output the data. A Read command can be issued in one bank while programming or erasing in the other bank. However if a Read command is issued to a bank currently executing a program or erase operation the command will be ignored. When a device Reset occurs, the memory defaults to Read mode. Read Status Register Command A bank's Status Register indicates when a program or erase operation is complete and the success or failure of operation itself. Issue a Read Status Register command to read the Status Register content of the addressed bank. The status of the other bank is not affected by the command. The Read Status Register command can be issued at any time, even during program or erase operations. The following Read operations output the content of the Status Register of the addressed bank. The Status Register is latched on the falling edge of E or G signals, and can be read until E or G returns to V IH. Either E or G must be toggled to update the latched data. See Table 15 for the description of the Status Register Bits. This mode supports asynchronous or single synchronous reads only. Read Electronic Signature Command The Read Electronic Signature command reads the Manufacturer and Device Codes and the Block Locking Status, or the Protection Register.
The Read Electronic Signature command consists of one write cycle to an address within the bottom bank. A subsequent read operation in the address of the bottom bank will output the Manufacturer Code, the Device Code, the protection Status of Blocks of the bottom bank, the Die Revision Code, the Protection Register, or the Read Configuration Register (see Table 11). If the first write cycle of Read Electronic Signature command is issued to an address within the top bank, a subsequent read operation in an address of the top bank will output the protection Status of blocks of the top bank. The status of the other bank is not affected by the command (see Table 7). This mode supports asynchronous or single synchronous reads only. See Tables 8, 9, 10 and 11 for the valid addresses. Read CFI Query Command The Read CFI Query Command is used to read data from the Common Flash Interface (CFI) Memory Area, located in the bottom bank. One Bus Write cycle, addressed to the bottom bank, is required to issue the Read Query Command. Once the command is issued subsequent Bus Read operations in the bottom bank read from the Common Flash Interface Memory Area. The status of the top bank is not affected by the command (see Table 7). After issuing a Read CFI Query command, a Read command should be issued to return the bank to read mode. See Appendix B, Common Flash Interface, Tables 29, 30, 31, 32, 33, 34 and 35 for details on the information contained in the Common Flash Interface memory area. Clear Status Register Command The Clear Status Register command can be used to reset (set to `0') bits 1, 3, 4 and 5 in the Status Register of the addressed bank'. One bus write cycle is required to issue the Clear Status Register command. After the Clear Status Register command the bank returns to read mode. The bits in the Status Register do not automatically return to `0' when a new Program or Erase command is issued. The error bits in the Status Register should be cleared before attempting a new Program or Erase command. Block Erase Command The Block Erase command can be used to erase a block. It sets all the bits within the selected block to '1'. All previous data in the block is lost. If the block is protected then the Erase operation will abort, the data in the block will not be changed and the Status Register will output the error. It is not necessary to pre-program the block as the Pro-
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gram/Erase Controller does it automatically before erasing. Two Bus Write cycles are required to issue the command. s The first bus cycle sets up the Erase command. s The second latches the block address in the internal state machine and starts the Program/ Erase Controller. If the second bus cycle is not Write Erase Confirm (D0h), Status Register bits b4 and b5 are set and the command aborts. Erase aborts if Reset turns to VIL. As data integrity cannot be guaranteed when the Erase operation is aborted, the block must be erased again. Once the command is issued the device outputs the Status Register data when any address within the bank is read. At the end of the operation the bank will remain in Read Status Register until a Read command is issued. During Erase operations the bank containing the block being erased will only accept the Read Status Register command and the Program/Erase Suspend command, all other commands will be ignored. Typical Erase times are given in Table 12, Program, Erase Times and Program/Erase Endurance Cycles. See Appendix B, Figure 22, Block Erase Flowchart and Pseudo Code, for a suggested flowchart for using the Block Erase command. Bank Erase Command The Bank Erase command can be used to erase a bank. It sets all the bits within the selected bank to '1'. All previous data in the bank is lost. The Bank Erase command will ignore any protected blocks within the bank. If the bank is protected then the Erase operation will abort, the data in the bank will not be changed and the Status Register will output the error. Two Bus Write cycles are required to issue the command. s The first bus cycle sets up the Bank Erase command. s The second latches the bank address in the internal state machine and starts the Program/ Erase Controller. If the second bus cycle is not Write Bank Erase Confirm (D0h), Status Register bits b4 and b5 are set and the command aborts. Erase aborts if Reset turns to VIL. As data integrity cannot be guaranteed when the Erase operation is aborted, the bank must be erased again. Once the command is issued the device outputs the Status Register data when any address within the bank is read. At the end of the operation the bank will remain in Read Status Register until a Read command is issued. During Erase operations the bank being erased will only accept the Read Status Register command and the Program/Erase Suspend command, all other commands will be ignored. Typical Erase times are given in Table 12, Program, Erase Times and Program/Erase Endurance Cycles. Program Command The memory array can be programmed word-byword. Only one bank can be programmed at any one time. The other bank must be in Read mode or Erase Suspend. Two bus write cycles are required to issue the Program Command. s The first bus cycle sets up the Program command. s The second latches the Address and the Data to be written and starts the Program/Erase Controller. After programming has started, Read operations in the bank being programmed output the Status Register content. During Program operations the bank being programmed will only accept the Read Status Register command and the Program/Erase Suspend command. Typical Program times are given in Table 12, Program, Erase Times and Program/Erase Endurance Cycles. Programming aborts if Reset goes to VIL. As data integrity cannot be guaranteed when the program operation is aborted, the block containing the memory location must be erased and reprogrammed. See Appendix B, Figure 18, Program Flowchart and Pseudo Code, for the flowchart for using the Program command. Double Word Program Command This feature is offered to improve the programming throughput, writing a page of two adjacent words in parallel. The two words must differ only for the address A0. Only one bank can be programmed at any one time. The other bank must be in Read mode or Erase Suspend. Programming should not be attempted when VPP is not at VPPH. The command can be executed if VPP is below VPPH but the result is not guaranteed. Three bus write cycles are necessary to issue the Double Word Program command. s The first bus cycle sets up the Double Word Program Command. s The second bus cycle latches the Address and the Data of the first word to be written. s The third bus cycle latches the Address and the Data of the second word to be written and starts the Program/Erase Controller.
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Read operations in the bank being programmed output the Status Register content after the programming has started. During Double Word Program operations the bank being programmed will only accept the Read Status Register command and the Program/Erase Suspend command. Typical Program times are given in Table 12, Program, Erase Times and Program/Erase Endurance Cycles. Programming aborts if Reset goes to VIL. As data integrity cannot be guaranteed when the program operation is aborted, the block containing the memory location must be erased and reprogrammed. See Appendix B, Figure 19, Double Word Program Flowchart and Pseudo Code, for the flowchart for using the Double Word Program command. Quadruple Word Program Command This feature is offered to improve the programming throughput, writing a page of four adjacent words in parallel. The four words must differ only for the addresses A0 and A1. The first write cycle must be addressed to the bank to be programmed. Only one bank can be programmed at any one time. The other bank must be in Read mode or Erase Suspend. Programming should not be attempted when VPP is not at VPPH. The command can be executed if VPP is below VPPH but the result is not guaranteed. Five bus write cycles are necessary to issue the Quadruple Word Program command. s The first bus cycle sets up the Double Word Program Command. s The second bus cycle latches the Address and the Data of the first word to be written. s The third bus cycle latches the Address and the Data of the second word to be written. s The fourth bus cycle latches the Address and the Data of the third word to be written. s The fifth bus cycle latches the Address and the Data of the fourth word to be written and starts the Program/Erase Controller. Read operations to the bank being programmed output the Status Register content after the programming has started. Programming aborts if Reset goes to VIL. As data integrity cannot be guaranteed when the program operation is aborted, the block containing the memory location must be erased and reprogrammed. During Quadruple Word Program operations the bank being programmed will only accept the Read Status Register command and the Program/Erase Suspend command. Typical Program times are given in Table 12, Program, Erase Times and Program/Erase Endurance Cycles. See Appendix B, Figure 20, Quadruple Word Program Flowchart and Pseudo Code, for the flowchart for using the Quadruple Word Program command. Program/Erase Suspend Command The Program/Erase Suspend command is used to pause a Program or Erase operation. One bus write cycle is required to issue the Program/Erase command and pause the Program/Erase controller. The command must be addressed to the bank containing the program or erase operation. During Program/Erase Suspend the Command Interface will accept the Program/Erase Resume, Read, Read Status Register, Read Electronic Signature and Read CFI Query commands. Additionally, if the suspend operation was Erase then the Program, Block Lock, Block Lock-Down or Protection Program commands will also be accepted. The block being erased may be protected by issuing the Block Lock, Block Lock-Down or Protection Program commands. Only the blocks not being erased may be read or programmed correctly. When the Program/Erase Resume command is issued the operation will complete. During a Program/Erase Suspend, the device can be placed in a pseudo-standby mode by taking Chip Enable to V IH. Program/Erase is aborted if Reset turns to VIL. See Appendix B, Figure 21, Program Suspend & Resume Flowchart and Pseudo Code, and Figure 23, Erase Suspend & Resume Flowchart and Pseudo Code for flowcharts for using the Program/ Erase Suspend command. Program/Erase Resume Command The Program/Erase Resume command can be used to restart the Program/Erase Controller after a Program/Erase Suspend command has paused it. One Bus Write cycle is required to issue the command. The command must be addressed to the bank containing the program or erase operation. Once the command is issued subsequent Bus Read operations read the Status Register. If a Program command is issued during a Block Erase Suspend, then the erase cannot be resumed until the programming operation has completed. It is possible to accumulate suspend operations. For example: suspend an erase operation, start a programming operation, suspend the programming operation then read the array. See Appendix B, Figure 21, Program Suspend & Resume Flowchart and Pseudo Code, and Figure 23, Erase Suspend & Resume Flowchart and Pseudo Code for flowcharts for using the Program/Erase Resume command.
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Protection Register Program Command The Protection Register Program command is used to Program the 64 bit user One-Time-Programmable (OTP) segment of the Protection Register. The segment is programmed 16 bits at a time. When shipped all bits in the segment are set to `1'. The user can only program the bits to `0'. Two write cycles are required to issue the Protection Register Program command. s The first bus cycle sets up the Protection Register Program command. s The second latches the Address and the Data to be written to the Protection Register and starts the Program/Erase Controller. Read operations output the Status Register content after the programming has started. The segment can be protected by programming bit 1 of the Protection Lock Register. Bit 1 of the Protection Lock Register protects bit 2 of the Protection Lock Register. Programming bit 2 of the Protection Lock Register will result in a permanent protection of the Security Block (see Figure 5, Security Block and Protection Register Memory Map). Attempting to program a previously protected Protection Register will result in a Status Register error. The protection of the Protection Register and/or the Security Block is not reversible. The Protection Register Program cannot be suspended. See Appendix B, Figure 25, Protection Register Program Flowchart and Pseudo Code, for a flowchart for using the Protection Register Program command. Block Lock Command The Block Lock command is used to lock a block and prevent Program or Erase operations from changing the data in it. All blocks are locked at power-up or reset. Two Bus Write cycles are required to issue the Block Lock command. s The first bus cycle sets up the Block Lock command. s The second Bus Write cycle latches the block address. The lock status can be monitored for each block using the Read Electronic Signature command. Table. 14 shows the Lock Status after issuing a Block Lock command. The Block Lock bits are volatile, once set they remain set until a hardware reset or power-down/ power-up. They are cleared by a Blocks Unlock command. Refer to the section, Block Locking, for a detailed explanation. See Appendix B, Figure 24, Locking Operations Flowchart and Pseudo Code, for a flowchart for using the Lock command. Block Unlock Command The Blocks Unlock command is used to unlock a block, allowing the block to be programmed or erased. Two Bus Write cycles are required to issue the Blocks Unlock command. s The first bus cycle sets up the Block Unlock command. s The second Bus Write cycle latches the block address. The lock status can be monitored for each block using the Read Electronic Signature command. Table. 13 shows the protection status after issuing a Block Unlock command. Refer to the section, Block Locking, for a detailed explanation and Appendix B, Figure 24, Locking Operations Flowchart and Pseudo Code, for a flowchart for using the Unlock command. Block Lock-Down Command A locked block cannot be Programmed or Erased, or have its protection status changed when WP is low, VIL. When WP is high, VIH, the Lock-Down function is disabled and the locked blocks can be individually unlocked by the Block Unlock command. Two Bus Write cycles are required to issue the Block Lock-Down command. s The first bus cycle sets up the Block Lock command. s The second Bus Write cycle latches the block address. The lock status can be monitored for each block using the Read Electronic Signature command. Locked-Down blocks revert to the locked (and not locked-down) state when the device is reset on power-down. Table. 14 shows the Lock Status after issuing a Block Lock-Down command. Refer to the section, Block Locking, for a detailed explanation and Appendix B, Figure 24, Locking Operations Flowchart and Pseudo Code, for a flowchart for using the Lock-Down command. Set Burst Configuration Register Command. The Set Burst Configuration Register command is used to write a new value to the Burst Configuration Control Register which defines the burst length, type, X latency, Synchronous/Asynchronous Read mode and the valid Clock edge configuration. Two Bus Write cycles are required to issue the Set Burst Configuration Register command. The first cycle writes the setup command and the address corresponding to the Set Burst Configuration Register content. The second cycle writes the Burst Configuration Register data and the confirm command. Once the command is issued the memory returns to Read mode as if a Read Memory Array command had been issued.
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The value for the Burst Configuration Register is always presented on A0-A15. M0 is on A0, M1 on A1, etc.; the other address bits are ignored. Table 6. Commands
Cycles Bus Write Operations 1st Cycle Op. Add Data
BKA BKA ESA QA BA BKA PA
Commands
2nd Cycle Op. Add
RA BKA
3rd Cycle
4th Cycle
5th Cycle
Data
RD SRD IDh QD D0h D0h PD
Op. Add Data Op.
Add Data Op. Add Data
Read Memory Array Read Status Register Read Electronic Signature Read CFI Query Block Erase Bank Erase Program Double Word Program(3) Quadruple Word Program(4) Clear Status Register Program/Erase Suspend Program/Erase Resume Block Lock Block Unlock Block Lock-Down Protection Register Program Set Burst Configuration Register
1+ Write 1+ Write 1+ Write 1+ Write 2 2 2 Write Write Write
FFh Read 70h 90h 98h 20h 80h 40h or 10h 30h Read
Read ESA(2) Read Write Write Write QA BA BKA PA
3
Write
PA1
Write
PA1
PD1
Write
PA2
PD2
5 1 1 1 2 2 2 2
Write Write Write Write Write Write Write Write
PA1 BKA BKA BKA BA BA BA PRA
55h 50h B0h D0h 60h 60h 60h
Write
PA1
PD1
Write
PA2
PD2 Write
PA3
PD3 Write
PA4
PD4
Write Write Write
BA BA BA PRA
01h D0h 2Fh PRD
C0h Write
2
Write BCRA 60h
Write BCRA
03h
Note: 1. X = Don't Care, RA=Read Address, RD=Read Data, SRD=Status Register Data, ESA= Electronic Signature Address, ID=Identifier (Manufacture and Device Code), QA=Query Address, QD=Query Data, BA=Block Address, PA=Program Address, PD=Program Data, PRA=Protection Register Address, PRD=Protection Register Data, BCRA=Burst Configuration Register Address, BCRD=Burst Configuration Register Data. 2. The signature addresses are listed in Tables 8, 9 and 10. 3. Program Addresses 1 and 2 must be consecutive Addresses differing only for A0. 4. Program Addresses 1,2,3 and 4 must be consecutive Addresses differing only for A0 and A1.
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Table 7. Dual Bank Operations
Commands allowed in the other bank Status of one bank Read Array Yes - Yes Yes Yes Yes Read Status Yes - Yes Yes Yes Yes Read CFI Yes - Yes Yes Yes Yes Program Yes - - - - Yes Erase/ Erase Resume Yes - - - - - Program Suspend Yes - - - - Yes Erase Suspend Yes - - - - - Lock Unlock Yes - Yes Yes Yes Yes
Idle Reading Programming Erasing Program Suspended Erase Suspended
Note: 1. For detailed description of command see Table 6, 36 and 37. 2. There is a Status Register for each bank; Status Register indicates bank state, not P/E.C. status. 3. Command must be written to an address within the block targeted by that command.
Table 8. Read Electronic Signature
Code Manufacturer Code M58CR032C Device Code M58CR032D VIL VIL VIH VIL VIH ESA (2) 88C9h
Note: 1. Addresses are latched on the rising edge of L input. 2. ESA means Electronic Signature Address (see Read Electronic Signature)
Device
E VIL VIL
G VIL VIL
W VIH VIH
A1 VIL VIL
A0 VIL VIH
Other Addresses ESA (2) ESA (2)
DQ15-DQ0 0020h 88C8h
Table 9. Read Block Protection
Block Status Locked Block Unlocked Block Locked and Locked-Down Block Unlocked and Locked-Down E VIL VIL VIL VIL G VIL VIL VIL VIL W VIH VIH VIH VIH A0 VIL VIL VIL VIL A1 VIH VIH VIH VIH Other Address BA (3) BA (3) BA (3) BA (3) DQ15-DQ0 0001 0000 0003 0002
Note: 1. Addresses are latched on the rising edge of L input. 2. A locked block can only be unlocked with WP at VIH. 3. BA means Block Address. First cycle command address should indicate the bank of the block address.
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Table 10. Read Protection Register
Word Lock Unique ID 0 Unique ID 1 Unique ID 2 Unique ID 3 OTP 0 OTP 1 OTP 2 OTP 3 E VIL VIL VIL VIL VIL VIL VIL VIL VIL G VIL VIL VIL VIL VIL VIL VIL VIL VIL W VIH VIH VIH VIH VIH VIH VIH VIH VIH A20-16 X (2) X (2) X (2) X (2) X (2) X (2) X (2) X (2) X (2) A15-8 X (2) X (2) X (2) X (2) X (2) X (2) X (2) X (2) X (2) A7-0 80h 81h 82h 83h 84h 85h 86h 87h 88h DQ15-8 00h ID data ID data ID data ID data OTP data OTP data OTP data OTP data DQ7-3 00000B ID data ID data ID data ID data OTP data OTP data OTP data OTP data DQ2 Security prot.data ID data ID data ID data ID data OTP data OTP data OTP data OTP data DQ1 OTP prot.data ID data ID data ID data ID data OTP data OTP data OTP data OTP data DQ0 0 ID data ID data ID data ID data OTP data OTP data OTP data OTP data
Note: 1. Addresses are latched on the rising edge of L input. 2. X = Don't care.
Table 11. Identifier Codes
Code Manufacturer Code Top (M58CR032C) Device Code Bottom (M58CR032D) Lock Unlocked Block Protection Locked and Locked-Down Unlocked and Locked-Down Die Revision Code Burst Configuration Register Lock Protection Register Protection Register Bank Address + 03 Bank Address + 05 Bank Address + 80 Bank Address + 81 Bank Address + 88 Bank Address + 02 0003 0002 DRC BCR LPR PR Bank Address + 01 88C9 0001 0000 Address (h) Bank Address + 00 Data (h) 0020 88C8
Note: DRC=Die Revision Code, BCR=Burst Configuration Register, LPR= Lock Protection Register, PR=Protection Register (Unique Device Number and User Programmable OTP).
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Table 12. Program, Erase Times and Program, Erase Endurance Cycles
Parameter Parameter Block (4 KWord) Erase(2) Preprogrammed Main Block (32 KWord) Erase Not Preprogrammed Preprogrammed Bank A (8Mbit) Erase Not Preprogrammed Preprogrammed VPP = VDD Bank B (24Mbit) Erase Not Preprogrammed Parameter Block (4 KWord) Program(3) Main Block (32 KWord) Program(3) Word Program (3) Program Suspend Latency Erase Suspend Latency Main Blocks Program/Erase Cycles (per Block) Parameter Blocks Parameter Block (4 KWord) Erase Main Block (32 KWord) Erase Bank A (8Mbit) Erase Bank B (24Mbit) Erase 4Mbit Program VPP = VPPH Quadruple Word 100,000 0.3 0.9 6.5 19.5 510 8 8 32 64 256 1000 2500 100 2.5 4 cycles s s s s ms s ms ms ms ms cycles cycles 100,000 27 40 300 10 5 5 10 100 10 20 s ms ms s s s cycles 9 16.5 s s 1.1 5.5 4 s s Condition Min Typ 0.3 0.8 Typical after 100k W/E Cycles 1 3 Max 2.5 4 Unit s s
Word/ Double Word/ Quadruple Word Program(3) Parameter Block (4 KWord) Program(3) Quadruple Word Word Quadruple Word Word Main Blocks Program/Erase Cycles (per Block) Parameter Blocks
Main Block (32 KWord) Program(3)
Note: 1. TA = -40 to 85C; VDD = 1.65V to 2V; VDDQ = 1.65V to 3.3V. 2. The difference between Preprogrammed and not preprogrammed is not significant (30ms). 3. Excludes the time needed to execute the command sequence.
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BLOCK LOCKING The M58CR032 features an instant, individual block locking scheme that allows any block to be locked or unlocked with no latency. This locking scheme has three levels of protection. s Lock/Unlock - this first level allows softwareonly control of block locking.
s
Lock-Down - this second level requires hardware interaction before locking can be changed. VPP VPPLK - the third level offers a complete hardware protection against program and erase on all blocks.
s
For all devices the protection status of each block can be set to Locked, Unlocked, and Lock-Down. Table 14, defines all of the possible protection states (WP, DQ1, DQ0), and Appendix B, Figure 24, shows a flowchart for the locking operations. Reading a Block's Lock Status The lock status of every block can be read in the Read Electronic Signature mode of the device. To enter this mode write 90h to the device. Subsequent reads at the address specified in Table 9, will output the protection status of that block. The lock status is represented by DQ0 and DQ1. DQ0 indicates the Block Lock/Unlock status and is set by the Lock command and cleared by the Unlock command. It is also automatically set when entering Lock-Down. DQ1 indicates the Lock-Down status and is set by the Lock-Down command. It cannot be cleared by software, only by a hardware reset or power-down. The following sections explain the operation of the locking system. Locked State The default status of all blocks on power-up or after a hardware reset is Locked (states (0,0,1) or (1,0,1)). Locked blocks are fully protected from any program or erase. Any program or erase operations attempted on a locked block will return an error in the Status Register. The Status of a Locked block can be changed to Unlocked or Lock-Down using the appropriate software commands. An Unlocked block can be Locked by issuing the Lock command. Unlocked State Unlocked blocks (states (0,0,0), (1,0,0) (1,1,0)), can be programmed or erased. All unlocked blocks return to the Locked state after a hardware reset or when the device is powered-down. The status of an unlocked block can be changed to Locked or Locked-Down using the appropriate
software commands. A locked block can be unlocked by issuing the Unlock command. Lock-Down State Blocks that are Locked-Down (state (0,1,x))are protected from program and erase operations (as for Locked blocks) but their protection status cannot be changed using software commands alone. A Locked or Unlocked block can be Locked-Down by issuing the Lock-Down command. LockedDown blocks revert to the Locked state when the device is reset or powered-down. The Lock-Down function is dependent on the WP input pin. When WP=0 (VIL), the blocks in the Lock-Down state (0,1,x) are protected from program, erase and protection status changes. When WP=1 (V IH) the Lock-Down function is disabled (1,1,1) and Locked-Down blocks can be individually unlocked to the (1,1,0) state by issuing the software command, where they can be erased and programmed. These blocks can then be re-locked (1,1,1) and unlocked (1,1,0) as desired while WP remains high. When WP is low , blocks that were previously Locked-Down return to the Lock-Down state (0,1,x) regardless of any changes made while WP was high. Device reset or power-down resets all blocks , including those in Lock-Down, to the Locked state. Locking Operations During Erase Suspend Changes to block lock status can be performed during an erase suspend by using the standard locking command sequences to unlock, lock or lock-down a block. This is useful in the case when another block needs to be updated while an erase operation is in progress. To change block locking during an erase operation, first write the Erase Suspend command, then check the status register until it indicates that the erase operation has been suspended. Next write the desired Lock command sequence to a block and the lock status will be changed. After completing any desired lock, read, or program operations, resume the erase operation with the Erase Resume command. If a block is locked or locked-down during an erase suspend of the same block, the locking status bits will be changed immediately, but when the erase is resumed, the erase operation will complete. Locking operations cannot be performed during a program suspend. Refer to Appendix C, Command Interface State Table, for detailed information on which commands are valid during erase suspend.
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Table 13. Block Lock Status
Item Block Lock Configuration Block is Unlocked xx002 Block is Locked Block is Locked-Down DQ0=1 DQ1=1 Address Data LOCK DQ0=0
Table 14. Lock Status
Current Protection Status(1) (WP, DQ1, DQ0) Current State 1,0,0 1,0,1
(2)
Next Protection Status(1) (WP, DQ1, DQ0) After Block Lock Command 1,0,1 1,0,1 1,1,1 1,1,1 0,0,1 0,0,1 0,1,1 After Block Unlock Command 1,0,0 1,0,0 1,1,0 1,1,0 0,0,0 0,0,0 0,1,1 After Block Lock-Down Command 1,1,1 1,1,1 1,1,1 1,1,1 0,1,1 0,1,1 0,1,1 After WP transition 0,0,0 0,0,1 0,1,1 0,1,1 1,0,0 1,0,1 1,1,1 or 1,1,0 (3)
Program/Erase Allowed yes no yes no yes no no
1,1,0 1,1,1 0,0,0 0,0,1(2) 0,1,1
Note: 1. The lock status is defined by the write protect pin and by DQ1 (`1' for a locked-down block) and DQ0 (`1' for a locked block) as read in the Read Electronic Signature command with A1 = VIH and A0 = VIL. 2. All blocks are locked at power-up, so the default configuration is 001 or 101 according to WP status. 3. A WP transition to VIH on a locked block will restore the previous DQ0 value, giving a 111 or 110.
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M58CR032C, M58CR032D
STATUS REGISTER The M58CR032 has two Status Registers, one for each bank. The Status Registers provide information on the current or previous Program or Erase operations executed in each bank. The various bits convey information and errors on the operation. Issue a Read Status Register command to read the Status Register content of the addressed bank, refer to Read Status Register Command section for more details. To output the contents, the Status Register is latched on the falling edge of the Chip Enable or Output Enable signals, and can be read until Chip Enable or Output Enable returns to V IH. Either Chip Enable or Output Enable must be toggled to update the latched data. Bus Read operations from any address within the bank, always read the Status Register during Program and Erase operations. The bits in the Status Register are summarized in Table 15, Status Register Bits. Refer to Table 15 in conjunction with the following text descriptions. Program/Erase Controller Status (Bit 7). The Program/Erase Controller Status bit indicates whether the Program/Erase Controller is active or inactive in the addressed bank. When the Program/Erase Controller Status bit is Low (set to `0'), the Program/Erase Controller is active; when the bit is High (set to `1'), the Program/Erase Controller is inactive, and the device is ready to process a new command. The Program/Erase Controller Status is Low immediately after a Program/Erase Suspend command is issued until the Program/Erase Controller pauses. After the Program/Erase Controller pauses the bit is High . During Program, Erase, operations the Program/ Erase Controller Status bit can be polled to find the end of the operation. Other bits in the Status Register should not be tested until the Program/Erase Controller completes the operation and the bit is High. After the Program/Erase Controller completes its operation the Erase Status, Program Status, VPP Status and Block Lock Status bits should be tested for errors. Erase Suspend Status (Bit 6). The Erase Suspend Status bit indicates that an Erase operation has been suspended or is going to be suspended in the addressed block. When the Erase Suspend Status bit is High (set to `1'), a Program/Erase Suspend command has been issued and the memory is waiting for a Program/Erase Resume command. The Erase Suspend Status should only be considered valid when the Program/Erase Controller Status bit is High (Program/Erase Controller inactive). Bit 7 is set within 30s of the Program/Erase Sus-
pend command being issued therefore the memory may still complete the operation rather than entering the Suspend mode. When a Program/Erase Resume command is issued the Erase Suspend Status bit returns Low. Erase Status (Bit 5). The Erase Status bit can be used to identify if the memory has failed to verify that the block has erased correctly. When the Erase Status bit is High (set to `1'), the Program/ Erase Controller has applied the maximum number of pulses to the block and still failed to verify that the block has erased correctly. The Erase Status bit should be read once the Program/Erase Controller Status bit is High (Program/Erase Controller inactive). Once set High, the Erase Status bit can only be reset Low by a Clear Status Register command or a hardware reset. If set High it should be reset before a new Program or Erase command is issued, otherwise the new command will appear to fail. Program Status (Bit 4). The Program Status bit is used to identify a Program failure. When the Program Status bit is High (set to `1'), the Program/Erase Controller has applied the maximum number of pulses to the Byte and still failed to verify that it has programmed correctly. The Program Status bit should be read once the Program/Erase Controller Status bit is High (Program/Erase Controller inactive). Once set High, the Program Status bit can only be reset Low by a Clear Status Register command or a hardware reset. If set High it should be reset before a new command is issued, otherwise the new command will appear to fail. VPP Status (Bit 3). The VPP Status bit can be used to identify an invalid voltage on the VPP pin during Program and Erase operations. The VPP pin is only sampled at the beginning of a Program or Erase operation. Indeterminate results can occur if V PP becomes invalid during an operation. When the VPP Status bit is Low (set to `0'), the voltage on the V PP pin was sampled at a valid voltage; when the V PP Status bit is High (set to `1'), the VPP pin has a voltage that is below the V PP Lockout Voltage, VPPLK, the memory is protected and Program and Erase operations cannot be performed. Once set High, the V PP Status bit can only be reset Low by a Clear Status Register command or a hardware reset. If set High it should be reset before a new Program or Erase command is issued, otherwise the new command will appear to fail. Program Suspend Status (Bit 2). The Program Suspend Status bit indicates that a Program operation has been suspended in the addressed block. When the Program Suspend Status bit is High (set to `1'), a Program/Erase Suspend command has
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been issued and the memory is waiting for a Program/Erase Resume command. The Program Suspend Status should only be considered valid when the Program/Erase Controller Status bit is High (Program/Erase Controller inactive). Bit 2 is set within 5s of the Program/Erase Suspend command being issued therefore the memory may still complete the operation rather than entering the Suspend mode. When a Program/Erase Resume command is issued the Program Suspend Status bit returns Low. Block Protection Status (Bit 1). The Block Protection Status bit can be used to identify if a Program or Erase operation has tried to modify the contents of a locked block. When the Block Protection Status bit is High (set to `1'), a Program or Erase operation has been attempted on a locked block. Once set High, the Block Protection Status bit can only be reset Low by a Clear Status Register command or a hardware reset. If set High it should be reset before a new command is issued, otherwise the new command will appear to fail. Reserved (Bit 0). Bit 0 of the Status Register is reserved. Its value must be masked. Note: Refer to Appendix B, Flowcharts and Pseudo Codes, for using the Status Register.
Table 15. Status Register Bits
Bit 7 Name P/E.C. Status '0' '1' 6 Erase Suspend Status '0' '1' 5 Erase Status '0' '1' 4 Program Status '0' '1' 3 VPP Status '0' '1' 2 Program Suspend Status '0' '1' 1 0 Block Protection Status '0' Reserved No operation to protected blocks In Progress or Completed Program/Erase on protected Block, Abort Program Success VPP Invalid, Abort VPP OK Suspended Erase Success Program Error In progress or Completed Erase Error Busy Suspended Logic Level '1' Ready Definition
Note: Logic level '1' is High, '0' is Low.
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M58CR032C, M58CR032D
MAXIMUM RATING Stressing the device above the rating listed in the Absolute Maximum Ratings table may cause permanent damage to the device. These are stress ratings only and operation of the device at these or any other conditions above those indicated in the Operating sections of this specification is not imTable 16. Absolute Maximum Ratings
Symbol TA TBIAS TSTG VIO (1) VDD, VDDQ VPP Parameter Ambient Operating Temperature Temperature Under Bias Storage Temperature Input or Output Voltage Supply Voltage Program Voltage Value -40 to 85 -40 to 125 -55 to 155 -0.5 to VDDQ+0.5 -0.5 to 2.7 -0.5 to 13 Unit C C C V V V
plied. Exposure to Absolute Maximum Rating conditions for extended periods may affect device reliability. Refer also to the STMicroelectronics SURE Program and other relevant quality documents.
Note: 1. Minimum Voltage may undershoot to -2V during transition and for less than 20ns during transitions.
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M58CR032C, M58CR032D
DC AND AC PARAMETERS This section summarizes the operating measurement conditions, and the DC and AC characteristics of the device. The parameters in the DC and AC characteristics Tables that follow, are derived from tests performed under the Measurement
Conditions summarized in Table 17, Operating and AC Measurement Conditions. Designers should check that the operating conditions in their circuit match the operating conditions when relying on the quoted parameters.
Table 17. Operating and AC Measurement Conditions
M58CR032C, M58CR032D 85 Parameter Min VDD Supply Voltage VDDQ Supply Voltage Ambient Operating Temperature Load Capacitance (CL) Input Rise and Fall Times Input Pulse Voltages Input and Output Timing Ref. Voltages 0 to VDDQ VDDQ/2 1.8 1.8 - 40 30 4 0 to VDDQ VDDQ/2 Max 2.0 3.3 85 Min 1.65 1.65 - 40 30 4 0 to VDDQ VDDQ/2 Max 2.0 3.3 85 Min 1.65 1.65 - 40 30 4 Max 2.0 3.3 85 V V C pF ns V V 100 120 Units
Figure 9. AC Measurement I/O Waveform
Figure 10. AC Measurement Load Circuit
VDDQ / 2
VDDQ VDDQ/2 0V
AI90007
1N914
3.3k DEVICE UNDER TEST CL
OUT
CL includes JIG capacitance
AI90008
Table 18. Capacitance
Symbol CIN COUT Parameter Input Capacitance Output Capacitance Test Condition VIN = 0V VOUT = 0V Min Max 6 12 Unit pF pF
Note: Sampled only, not 100% tested.
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Table 19. DC Characteristics - Currents
Symbol ILI ILO Parameter Input Leakage Current Output Leakage Current Supply Current Asynchronous Read (f=6MHz) IDD1 Supply Current Synchronous Read (f=40MHz) Supply Current (Reset) Supply Current (Standby) Supply Current (Program) IDD4 (1) Supply Current (Erase) VPP = VDD Program/Erase in one Bank, Asynchronous Read in another Bank Program/Erase in one Bank, Synchronous Read in another Bank E = VDD 0.2V VPP = VPPH VPP Supply Current (Program) IPP1(1) VPP Supply Current (Erase) VPP = VDD VPP = VPPH VPP = VDD VPP = VPPH VPP VDD VPP VDD 10 13 20 26 mA mA VPP = VDD VPP = VPPH 10 8 20 15 mA mA Test Condition 0V VIN VDDQ 0V VOUT VDDQ E = VIL, G = VIH 4 Word 8 Word Continuous IDD2 IDD3 RP = VSS 0.2V E = VDD 0.2V VPP = VPPH 3 6 8 6 2 10 8 Min Typ Max 1 1 6 13 14 10 10 50 15 Unit A A mA mA mA mA A A mA
Supply Current IDD5 (1,2) (Dual Operations)
16
30
mA
IDD6(1)
Supply Current Program/ Erase Suspended (Standby)
10 2 0.2 2 0.2 100 0.2 0.2
50 5 5 5 5 400 5 5
A mA A mA A A A A
IPP2 IPP3(1)
VPP Supply Current (Read) VPP Supply Current (Standby)
Note: 1. Sampled only, not 100% tested. 2. VDD Dual Operation current is the sum of read and program or erase currents.
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Table 20. DC Characteristics - Voltages
Symbol VIL VIH VOL VOH VPP1 VPPH VPPLK VLKO VRPH Parameter Input Low Voltage Input High Voltage Output Low Voltage Output High Voltage VPP Program Voltage-Logic VPP Program Voltage Factory Program or Erase Lockout VDD Lock Voltage RP pin Extended High Voltage 1 3.3 IOL = 100A IOH = -100A Program, Erase Program, Erase VDDQ -0.1 1 11.4 1.8 12 1.95 12.6 0.9 Test Condition Min -0.5 VDDQ -0.4 Typ Max 0.4 VDDQ + 0.4 0.1 Unit V V V V V V V V V
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tAVAV VALID DATA tAVQV VALID ADDRESS tAVLH tLHAX VALID ADDRESS
DQ0-DQ15
A0-A20
Figure 11. Asynchronous Read AC Waveforms
L tLLLH tLLQV tELLH tELQV
E tEHQZ tELQX tEHQX
G tGLQV tGLQX tGHQX tGHQZ
AI90109
M58CR032C, M58CR032D
Note: Write Enable (W) = High.
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VALID ADDRESS VALID ADDRESS VALID ADDRESS tLHAX VALID ADDRESS VALID ADDRESS tLLQV tLLQV1 tGLQV VALID DATA tAVQV1 VALID DATA VALID DATA VALID DATA
AI90148
M58CR032C, M58CR032D
A2-A20
A0-A1
tAVLH
L
Figure 12. Asynchronous Page Read AC Waveforms
E
G
DQ0-DQ15
M58CR032C, M58CR032D
Table 21. Asynchronous Read AC Characteristics
M58CR032 Symbol Alt Parameter Test Condition Min tAVAV tAVLH tAVQV tAVQV1 tEHQX tEHQZ (1) tELLH tELQV (2) tELQX (1) tGHQX tGHQZ (1) tGLQV (2) tGLQX (1) tLHAX tLLLH tLLQV tLLQV1 tRC tAVAVDH tACC tPAGE tOH tHZ tELAVDH tCE tLZ tOH tDF tOE tOLZ tAVDHAX tAVDLAVDH tAVDLQV Address Valid to Next Address Valid Address valid to Latch Enable High Address Valid to Output Valid (Random) Address Valid to Output Valid (Page) Chip Enable High to Output Transition Chip Enable High to Output Hi-Z Chip Enable Low to Latch Enable High Chip Enable Low to Output Valid Chip Enable Low to Output Transition Output Enable High to Output Transition Output Enable High to Output Hi-Z Output Enable Low to Output Valid Output Enable Low to Output Transition Latch Enable High to Address Transition Latch Enable Pulse Width Latch Enable Low to Output Valid (Random) Latch Enable Low to Output Valid (Page) E = VIL, G = VIL G = VIH E = VIL, G = VIL E = VIL, G = VIL G = VIL G = VIL E = VIL, G = VIH G = VIL G = VIL E = VIL E = VIL E = VIL E = VIL E = VIL, G = VIH E = VIL, G = VIH E = VIL E = VIL 0 10 10 85 35 0 0 20 25 0 10 10 100 45 10 85 0 0 20 25 0 10 10 120 45 0 20 10 100 0 0 20 35 85 10 85 35 0 20 10 120 85 Max 100 Min 100 10 100 45 0 20 Max 120 Min 120 10 120 45 Max ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns Unit
Note: 1. Sampled only, not 100% tested. 2. G may be delayed by up to t ELQV - tGLQV after the falling edge of E without increasing tELQV .
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VALID VALID VALID VALID DATA tLLLH tKHQV tKHKL note 1 tKHKH tKHQX tKLKH tEHQX tEHQZ tGLQX tGHQX tGHQZ tKHQV note 2 note 3 tKHQX
AI90110
DQ0-DQ15
M58CR032C, M58CR032D
A0-A20
VALID ADDRESS
tAVLH
Figure 13. Synchronous Burst Read
L
tLLKH
tAVKH
K
tELKH
tKAXH
E
G tKHQV
WAIT
Note: 1. The number of clock cycles to be inserted depends upon the x-latency set in the burst configuration register. 2. WAIT signal can be configured to be active during wait state or one cycle below wait state. 3. WAIT signal is asserted only when burst length is configured as continuous (see Burst Read section for further information).
M58CR032C, M58CR032D
Table 22. Synchronous Burst Read AC Characteristics
M58CR032 Symbol Alt Parameter Test Condition Min tAVKH tELKH tKHKH tKHAX tKHKL tKLKH tKHQV tKHQX tLLKH tAVCLKH tCELCLKH tCLK tCLKHAX Address Valid to Clock High Chip Enable Low to Clock High Clock Period Clock High to Address Transition E = VIL, G = VIH 7 85 Max 100 Min 7 Max 120 Min 7 Max ns Unit
7 18 10 5 5 E = VIL, G = VIL E = VIL 4 14
7 18 10 5 5 14
7 25 10 5 5 18
ns ns ns ns ns ns
tCLKHCLKL Clock High to Clock Low tCLKLCLKH Clock Low to Clock High tCLKHQV tCLKHQX tAVDLCLKH Clock to Data Valid Clock to WAIT Valid Clock to Output Transition Clock to WAIT Transition Latch Enable Low to Clock High
4
4
ns
7
7
7
ns
Note: For other timings please refer to Table 21, Asynchronous Read AC Characteristics
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tAVAV DATA VALID ADDRESS VALID tAVLH tLLLH tWHLL tLHAX tDVWH tWHDX tWHWL tWLWH tELLH tELWL tWHEH tWHGL tWPVWH VALID tVPPHWH VPPH VPP1 tWHVPPL tWHWPV
AI90111
DQ0-DQ15
M58CR032C, M58CR032D
A0-A20
L
W
Figure 14. Write AC Waveforms, Write Enable Controlled
E
G
WP
tVDHEL
VPP
VDD
M58CR032C, M58CR032D
Table 23. Write AC Characteristics, Write Enable Controlled
M58CR032 Symbol Alt Parameter Min tAVAV tAVLH tDVWH tELLH tELWL tLHAX tLLLH tVDHEL tVPPHWH tWHDX tWHEH tWHGL tWHLL tWHVPPL tWHWL tWHWPV tWLWH tWPVWH tWP tDH tCH tOEH tVCS tCS tDS tWC Address Valid to Next Address Valid Address Valid to Latch Enable High Input Valid to Write Enable High Chip Enable Low to Latch Enable High Chip Enable Low to Write Enable Low Latch Enable High to Address Transition Latch Enable Pulse Width VDD High to Chip Enable Low VPP High to Write Enable High Write Enable High to Input Transition Write Enable High to Chip Enable High Write Enable High to Output Enable Low Write Enable High to Latch Enable Low Write Enable High to VPP Low tWPH Write Enable High to Write Enable Low Write Enable High to Write Protect Valid Write Enable Low to Write Enable High Write Protect Valid to Write Enable High 85 10 40 10 0 10 10 50 200 0 0 0 0 200 30 200 50 200 85 Max Min 100 10 40 10 0 10 10 50 200 0 0 0 0 200 30 200 50 200 100 Max Min 120 10 40 10 0 10 10 50 200 0 0 0 0 200 30 200 50 200 120 Max ns ns ns ns ns ns ns s ns ns ns ns ns ns ns ns ns ns Unit
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tAVAV DATA VALID ADDRESS VALID tAVLH tLLLH tLHEH tWHLL tLHAX tDVEH tEHDX tEHWH tELLH tELEH tWPHEH tEHWPL tVPPHEH VPP2 VPP1 tEHVPPL
AI90112
DQ0-DQ15
M58CR032C, M58CR032D
A0-A20
L
tWLEL
W
E
Figure 15. Write AC Waveforms, Chip Enable Controlled
G
WP
tVDHEL
VPP
VDD
M58CR032C, M58CR032D
Table 24. Write AC Characteristics, Chip Enable Controlled
M58CR032 Symbol Alt Parameter Min tAVAV tAVLH tDVEH tEHDX tEHEL tEHWH tELEH tELLH tLHAX tLHEH tLLLH tVDHEL tVPPHEH tEHVPPL tEHWPL tWLEL tWPHEH tWS tDS tDH tWC Address Valid to Next Address Valid Address Valid to Latch Enable High Input Valid to Chip Enable High Chip Enable High to Input Transition 85 10 40 0 30 0 60 10 10 10 10 50 200 200 200 0 200 85 Max Min 100 10 40 0 30 0 60 10 10 10 10 50 200 200 200 0 200 100 Max Min 120 10 40 0 30 0 60 10 10 10 10 50 200 200 200 0 200 120 Max ns ns ns ns ns ns ns ns ns ns ns s ns ns ns ns ns Unit
tCPH Chip Enable High to Chip Enable Low tWH tCP Chip Enable High to Write Enable High Chip Enable Low to Chip Enable High Chip Enable Low to Latch Enable High Latch Enable High to Address Transition Latch Enable High to Chip Enable High Latch Enable Pulse Width tVCS VDD High to Chip Enable Low VPP High to Chip Enable High Chip Enable High to VPP Low Chip Enable High to Write Protect Low Chip Enable Low to Chip Enable Low Write Protect High to Chip Enable High
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Figure 16. Reset and Power-up AC Waveforms
W, E, G
tPLWL tPLEL tPLGL
RP tVDHPH VDD, VDDQ Power-Up Reset
AI90013b
tPLPH
Table 25. Reset and Power-up AC Characteristics
Symbol tPLPH (1,2) tPLWL tPLEL tPLGL tVDHPH (3) Parameter RP Pulse Width During Program and Erase Reset Low to Device Enabled Other Conditions Supply Valid to Reset High 80 50 ns s Test Condition Min 50 10/20 Unit ns s
Note: 1. The device Reset is possible but not guaranteed if tPLPH < 100ns. 2. Sampled only, not 100% tested. 3. It is important to assert RP in order to allow proper CPU initialization during Power-up or System reset.
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M58CR032C, M58CR032D
PACKAGE MECHANICAL Figure 17. TFBGA56 6.5x10mm - 8x7 ball array, 0.75 mm pitch, Bottom View Package Outline
D D1 FD SD
FE
E
E1
e BALL "A1" ddd e A A1 b A2
BGA-Z20
Note: Drawing is not to scale.
Table 26. TFBGA56 6.5x10mm - 8x7 ball array, 0.75 mm pitch, Package Mechanical Data
millimeters Symbol Typ A A1 A2 b D D1 ddd E E1 e FD FE SD 10.000 4.500 0.750 0.625 2.750 0.375 9.900 - - - - - 0.790 0.400 6.500 5.250 0.350 6.400 - 0.450 6.600 - 0.100 10.100 - - - - - 0.3937 0.1772 0.0295 0.0246 0.1083 0.0148 0.3898 - - - - - Min 1.010 0.250 Max 1.200 0.400 0.0311 0.0157 0.2559 0.2067 0.0138 0.2520 - 0.0177 0.2598 - 0.0039 0.3976 - - - - - Typ Min 0.0398 0.0098 Max 0.0472 0.0157 inches
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PART NUMBERING Table 27. Ordering Information Scheme
Example: Device Type M58 Architecture C = Dual Bank, Burst Mode Operating Voltage R = VDD = 1.65V to 2.0V, VDDQ = 1.65V to 3.3V Device Function 032C = 32 Mbit (x16), Dual Bank: 1/4-3/4 partitioning, Top Boot 032D = 32 Mbit (x16), Dual Bank: 1/4-3/4 partitioning, Bottom Boot Speed 85 = 85 ns 100 = 100 ns 120 = 120 ns Package ZB = TFBGA56: 0.75 mm pitch Temperature Range 6 = -40 to 85C Option T = Tape & Reel packing M58CR032C 85 ZB 6 T
Devices are shipped from the factory with the memory content bits erased to '1'. For a list of available options (Speed, Package, etc....) or for further information on any aspect of this device, please contact the ST Sales Office nearest to you.
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M58CR032C, M58CR032D
REVISION HISTORY Table 28. Document Revision History
Date April 2001 23-OCT-2001 21-Mar-2002 Version -01 -02 -03 First Issue 85ns speed class added, document classified as Preliminary Data Document completely revised. Changes in CFI content, Program and Erase Times Table and DC Characteristics Table Revision numbering modified: a minor revision will be indicated by incrementing the digit after the dot, and a major revision, by incrementing the digit before the dot (revision version 03 equals 3.0). Latch Enable, L, logic level modified during Asynchronous Read/Write operations as shown in Table 3, Bus Operations. First X-Latency formula modified together with meaning of tAVK_CPU parameter in formula (under Burst Configuration Register Paragraph). Minimum VDD and VDDQ supply voltages reduced to 1.8V for 85ns class speed in Table 17, Operating and AC Measurement Conditions. `Number of identical-size erase block' parameters modified in Table 32, Device Geometry Definition. Revision Details
06-Sep-2002
3.1
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APPENDIX A. COMMON FLASH INTERFACE The Common Flash Interface is a JEDEC approved, standardized data structure that can be read from the Flash memory device. It allows a system software to query the device to determine various electrical and timing parameters, density information and functions supported by the memory. The system can interface easily with the device, enabling the software to upgrade itself when necessary. When the Read CFI Query Command is issued the device enters CFI Query mode and the data Table 29. Query Structure Overview
Offset 00h 10h 1Bh 27h P A Reserved CFI Query Identification String System Interface Information Device Geometry Definition Primary Algorithm-specific Extended Query table Alternate Algorithm-specific Extended Query table Sub-section Name Description Reserved for algorithm-specific information Command set ID and algorithm data offset Device timing & voltage information Flash device layout Additional information specific to the Primary Algorithm (optional) Additional information specific to the Alternate Algorithm (optional) Lock Protection Register Unique device Number and User Programmable OTP
structure is read from the memory. Tables 29, 30, 31, 32, 33, 34 and 35 show the addresses used to retrieve the data. The CFI data structure also contains a security area where a 64 bit unique security number is written (see Table 35, Security Code area). This area can be accessed only in Read mode by the final user. It is impossible to change the security number after it has been written by ST. Issue a Read command to return to Read mode.
80h
Security Code Area
Note: The Flash memory display the CFI data structure when CFI Query command is issued. In this table are listed the main sub-sections detailed in Tables 30, 31, 32, 33, 34 and 35. Query data are always presented on the lowest order data outputs.
Table 30. CFI Query Identification String
Offset 00h 01h 02h 03h 04h-0Fh 10h 11h 12h 13h 14h 15h 16h 17h 18h 19h 1Ah Sub-section Name 0020h 88C8h 88C9h reserved reserved reserved 0051h 0052h 0059h 0003h 0000h offset = P = 0039h 0000h 0000h 0000h value = A = 0000h 0000h Primary Algorithm Command Set and Control Interface ID code 16 bit ID code defining a specific algorithm Address for Primary Algorithm extended Query table (see Table 32) Alternate Vendor Command Set and Control Interface ID Code second vendor - specified algorithm supported Address for Alternate Algorithm extended Query table p = 39h NA NA Query Unique ASCII String "QRY" Manufacturer Code Device Code (M58CR032C/D) Reserved Reserved Reserved "Q" "R" "Y" Description Value ST Top Bottom
Note: Query data are always presented on the lowest - order data outputs (ADQ0-ADQ7) only. ADQ8-ADQ15 are `0'.
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Table 31. CFI Query System Interface Information
Offset 1Bh Data 0017h Description VDD Logic Supply Minimum Program/Erase or Write voltage bit 7 to 4 BCD value in volts bit 3 to 0 BCD value in 100 millivolts VDD Logic Supply Maximum Program/Erase or Write voltage bit 7 to 4 BCD value in volts bit 3 to 0 BCD value in 100 millivolts VPP [Programming] Supply Minimum Program/Erase voltage bit 7 to 4 HEX value in volts bit 3 to 0 BCD value in 100 millivolts VPP [Programming] Supply Maximum Program/Erase voltage bit 7 to 4 HEX value in volts bit 3 to 0 BCD value in 100 millivolts Typical time-out per single Byte/Word program = 2n s Typical time-out for Quadruple Word Program = 2n s Typical time-out per individual Block Erase = 2n ms Typical time-out for full Chip Erase = 2n ms Maximum time-out for Word Program = 2n times typical Maximum time-out for Quadruple Word = 2n times typical Maximum time-out per individual Block Erase = 2n times typical Maximum time-out for Chip Erase = 2n times typical Value 1.7V
1Ch
0020h
2V
1Dh
0017h
1.7V
1Eh 1Fh 20h 21h 22h 23h 24h 25h 26h
00C0h 0004h 0003h 000Ah 0000h 0003h 0004h 0002h 0000h
12V 16s 8s 1s NA 128s 128s 4s NA
Table 32. Device Geometry Definition
Offset Word Mode 27h 28h 29h 2Ah 2Bh 2Ch Data 0016h 0001h 0000h 0003h 0000h 0002h Description Device Size = 2n in number of Bytes Flash Device Interface Code description Maximum number of Bytes in multi-Byte program or page = 2n Number of Erase Block Regions within the device bit 7 to 0 = x = number of Erase Block Regions It specifies the number of regions within the device containing one or more contiguous Erase Blocks of the same size. Value 4 MByte x16 Async. 8 Byte
2
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M58CR032C, M58CR032D
Offset Word Mode 2Dh 2Eh M58CR032C 2Fh 30h 31h 32h 33h 34h 35h 38h 2Dh 2Eh M58CR032D 2Fh 30h 31h 32h 33h 34h 35h 38h
Data 003Eh 0000h 0000h 0001h 0007h 0000h 0020h 0000h 0000h 0007h 0000h 0020h 0000h 003Eh 0000h 0000h 0001h 0000h
Description Region 1 Information Number of identical-size erase block = 003Eh+1 Region 1 Information Block size in Region 1 = 0100h * 256 Bytes Region 2 Information Number of identical-size erase block = 0007h+1 Region 2 Information Block size in Region 2 = 0020h * 256 Bytes Reserved for future raise block region information Region 1 Information Number of identical-size erase block = 0007h+1 Region 1 Information Block size in Region 1 = 0020h * 256 Bytes Region 2 Information Number of identical-size erase block = 003Eh+1 Region 2 Information Block size in Region 2 = 0100h * 256 Bytes Reserved for future raise block region information
Value 63 64 KByte 8 8 KByte NA 8 8 KByte 63 64 KByte NA
Table 33. Primary Algorithm-Specific Extended Query Table
Offset (P)h = 39h Data 0050h 0052h 0049h (P+3)h = 3Ch (P+4)h = 3Dh (P+5)h = 3Eh 0031h 0030h 00E6h 0003h (P+7)h (P+8)h 0000h 0000h Major version number, ASCII Minor version number, ASCII Extended Query table contents for Primary Algorithm. Address (P+5)h contains less significant Byte. bit bit bit bit bit bit bit bit bit bit bit 0 1 2 3 4 5 6 7 8 9 10 to 31 Chip Erase supported (1 = Yes, 0 = No) Erase Suspend supported (1 = Yes, 0 = No) Program Suspend supported (1 = Yes, 0 = No) Legacy Lock/Unlock supported (1 = Yes, 0 = No) Queued Erase supported (1 = Yes, 0 = No) Instant individual block locking supported (1 = Yes, 0 = No) Protection bits supported (1 = Yes, 0 = No) Page mode read supported (1 = Yes, 0 = No) Synchronous read supported (1 = Yes, 0 = No) Simultaneous operation supported (1 = Yes, 0 = No) Reserved; undefined bits are `0'. If bit 31 is '1' then another 31 bit field of optional features follows at the end of the bit-30 field. No Yes Yes No No Yes Yes Yes Yes Yes Primary Algorithm extended Query table unique ASCII string "PRI" Description Value "P" "R" "I" "1" "0"
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M58CR032C, M58CR032D
Offset (P+9)h = 42h Data 0001h Description Supported Functions after Suspend Read Array, Read Status Register and CFI Query Yes bit 0 bit 7 to 1 (P+A)h = 43h (P+B)h 0003h 0000h Program supported after Erase Suspend (1 = Yes, 0 = No) Reserved; undefined bits are `0' Value
Block Protect Status Defines which bits in the Block Status Register section of the Query are implemented. Block protect Status Register Lock/Unlock bit active (1 = Yes, 0 = No) bit 1 Block Lock Status Register Lock-Down bit active (1 = Yes, 0 = No) bit 15 to 2 Reserved for future use; undefined bits are `0' bit 0
Yes Yes 1.8V
(P+C)h = 45h
0018h
VDD Logic Supply Optimum Program/Erase voltage (highest performance) bit 7 to 4 bit 3 to 0 HEX value in volts BCD value in 100 mV
(P+D)h = 46h
00C0h
VPP Supply Optimum Program/Erase voltage bit 7 to 4 bit 3 to 0 HEX value in volts BCD value in 100 mV
12V
(P+E)h = 47h (P+F)h (P+10)h (P+11)h (P+12)h
0000h
Reserved
Table 34. Burst Read Information
Offset (P+13)h = 4Ch Data 0003h Description Page-mode read capability bits 0-7 'n' such that 2n HEX value represents the number of readpage Bytes. See offset 28h for device word width to determine page-mode data output width. Number of synchronous mode read configuration fields that follow. Synchronous mode read capability configuration 1 bit 3-7 Reserved bit 0-2 'n' such that 2n+1 HEX value represents the maximum number of continuous synchronous reads when the device is configured for its maximum word width. A value of 07h indicates that the device is capable of continuous linear bursts that will output data until the internal burst counter reaches the end of the device's burstable address space. This field's 3-bit value can be written directly to the read configuration register bit 0-2 if the device is configured for its maximum word width. See offset 28h for word width to determine the burst data output width. Synchronous mode read capability configuration 2 Synchronous mode read capability configuration 3 Max operating clock frequency (MHz) Value 8 Byte
(P+14)h = 4Dh (P+15)h = 4Eh
0003h 0001h
3 4
(P+16)h = 4Fh (P+17)h = 50h (P+18)h = 51h
0002h 0007h 0036h
8 Cont. 54 MHz
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Offset (P+19)h = 52h Data 0001h Description Supported handshaking signal (WAIT pin) bit 0 bit 1 during Synchronous Read during Asynchronous Read (1 = Yes, 0 = No) (1 = Yes, 0 = No) Yes No Value
Table 35. Security Code Area
Offset Data Description Lock Protection Register bit 0: ST programmed, value 0 bit 1: OTP protection and bit 2 protection bit bit 2: Security Block Protection bit bits 3 - 15 reserved
80h
LPR
81h 82h 83h 84h 85h 86h 87h 88h
ID data 64 bits: unique device number
OTP data
64 bits: User Programmable OTP
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APPENDIX B. FLOWCHARTS AND PSEUDO CODES Figure 18. Program Flowchart and Pseudo Code
Start
Write 40h or 10h
program_command (addressToProgram, dataToProgram) {: writeToFlash (any_address, 0x40) ; /*or writeToFlash (any_address, 0x10) ; */ writeToFlash (addressToProgram, dataToProgram) ; /*Memory enters read status state after the Program Command*/ do { status_register=readFlash (any_address) ; /* E or G must be toggled*/
Write Address & Data
Read Status Register
b7 = 1 YES b3 = 0 YES b4 = 0 YES b1 = 0 YES End
NO } while (status_register.b7== 0) ;
NO
VPP Invalid Error (1, 2)
if (status_register.b3==1) /*VPP invalid error */ error_handler ( ) ;
NO
Program Error (1, 2)
if (status_register.b4==1) /*program error */ error_handler ( ) ;
NO
Program to Protected Block Error (1, 2)
if (status_register.b1==1) /*program to protect block error */ error_handler ( ) ;
}
AI090014b
Note: 1. Status check of b1 (Protected Block), b3 (V PP Invalid) and b4 (Program Error) can be made after each program operation or after a sequence. 2. If an error is found, the Status Register must be cleared before further Program/Erase Controller operations.
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Figure 19. Double Word Program Flowchart and Pseudo code
Start
Write 30h
Write Address 1 & Data 1 (3)
Write Address 2 & Data 2 (3)
double_word_program_command (addressToProgram1, dataToProgram1, addressToProgram2, dataToProgram2) { writeToFlash (any_address, 0x30) ; writeToFlash (addressToProgram1, dataToProgram1) ; /*see note (3) */ writeToFlash (addressToProgram2, dataToProgram2) ; /*see note (3) */ /*Memory enters read status state after the Program command*/ do { status_register=readFlash (any_address) ; /* E or G must be toggled*/
Read Status Register
b7 = 1 YES b3 = 0 YES b4 = 0 YES b1 = 0 YES End
NO } while (status_register.b7== 0) ;
NO
VPP Invalid Error (1, 2)
if (status_register.b3==1) /*VPP invalid error */ error_handler ( ) ;
NO
Program Error (1, 2)
if (status_register.b4==1) /*program error */ error_handler ( ) ;
NO
Program to Protected Block Error (1, 2)
if (status_register.b1==1) /*program to protect block error */ error_handler ( ) ;
}
AI090015b
Note: 1. Status check of b1 (Protected Block), b3 (V PP Invalid) and b4 (Program Error) can be made after each program operation or after a sequence. 2. If an error is found, the Status Register must be cleared before further Program/Erase operations. 3. Address 1 and Address 2 must be consecutive addresses differing only for bit A0.
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M58CR032C, M58CR032D
Figure 20. Quadruple Word Program Flowchart and Pseudo Code
Start
Write 55h
Write Address 1 & Data 1 (3)
quadruple_word_program_command (addressToProgram1, dataToProgram1, addressToProgram2, dataToProgram2, addressToProgram3, dataToProgram3, addressToProgram4, dataToProgram4) { writeToFlash (any_address, 0x55) ; writeToFlash (addressToProgram1, dataToProgram1) ; /*see note (3) */
Write Address 2 & Data 2 (3)
writeToFlash (addressToProgram2, dataToProgram2) ; /*see note (3) */ writeToFlash (addressToProgram3, dataToProgram3) ; /*see note (3) */ writeToFlash (addressToProgram4, dataToProgram4) ; /*see note (3) */
Write Address 3 & Data 3 (3)
Write Address 4 & Data 4 (3)
/*Memory enters read status state after the Program command*/ do { status_register=readFlash (any_address) ; /* E or G must be toggled*/
Read Status Register
b7 = 1 YES b3 = 0 YES b4 = 0 YES b1 = 0 YES End
NO } while (status_register.b7== 0) ;
NO
VPP Invalid Error (1, 2)
if (status_register.b3==1) /*VPP invalid error */ error_handler ( ) ;
NO
Program Error (1, 2)
if (status_register.b4==1) /*program error */ error_handler ( ) ;
NO
Program to Protected Block Error (1, 2)
if (status_register.b1==1) /*program to protect block error */ error_handler ( ) ;
}
AI05283
Note: 1. Status check of b1 (Protected Block), b3 (V PP Invalid) and b4 (Program Error) can be made after each program operation or after a sequence. 2. If an error is found, the Status Register must be cleared before further Program/Erase operations. 3. Address 1 to Address 4 must be consecutive addresses differing only for bits A0 and A1.
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Figure 21. Program Suspend & Resume Flowchart and Pseudo Code
Start program_suspend_command ( ) { writeToFlash (any_address, 0xB0) ; writeToFlash (any_address, 0x70) ; /* read status register to check if program has already completed */ Write 70h do { status_register=readFlash (any_address) ; /* E or G must be toggled*/
Write B0h
Read Status Register
b7 = 1 YES b2 = 1 YES Write FFh
NO
} while (status_register.b7== 0) ;
NO
Program Complete
if (status_register.b2==0) /*program completed */ { writeToFlash (any_address, 0xFF) ; read_data ( ) ; /*read data from another block*/ /*The device returns to Read Array (as if program/erase suspend was not issued).*/
Read data from another address
} else { writeToFlash (any_address, 0xFF) ; read_data ( ); /*read data from another address*/ writeToFlash (any_address, 0xD0) ; /*write 0xD0 to resume program*/ } } Read Data
Write D0h
Write FFh
Program Continues
AI90016b
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Figure 22. Block Erase Flowchart and Pseudo Code
Start erase_command ( blockToErase ) { writeToFlash (any_address, 0x20) ; writeToFlash (blockToErase, 0xD0) ; /* only A12-A20 are significannt */ /* Memory enters read status state after the Erase Command */
Write 20h
Write Block Address & D0h
Read Status Register
do { status_register=readFlash (any_address) ; /* E or G must be toggled*/
b7 = 1
NO } while (status_register.b7== 0) ;
YES b3 = 0 YES b4, b5 = 1 NO b5 = 0 YES b1 = 0 YES End }
AI90017b
NO
VPP Invalid Error (1)
if (status_register.b3==1) /*VPP invalid error */ error_handler ( ) ;
YES
Command Sequence Error (1)
if ( (status_register.b4==1) && (status_register.b5==1) ) /* command sequence error */ error_handler ( ) ;
NO
Erase Error (1)
if ( (status_register.b5==1) ) /* erase error */ error_handler ( ) ;
NO
Erase to Protected Block Error (1)
if (status_register.b1==1) /*program to protect block error */ error_handler ( ) ;
Note: If an error is found, the Status Register must be cleared before further Program/Erase operations.
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Figure 23. Erase Suspend & Resume Flowchart and Pseudo Code
Start
Write B0h
erase_suspend_command ( ) { writeToFlash (any_address, 0xB0) ; writeToFlash (any_address, 0x70) ; /* read status register to check if erase has already completed */
Write 70h
Read Status Register
do { status_register=readFlash (any_address) ; /* E or G must be toggled*/
b7 = 1 YES b6 = 1 YES Write FFh
NO
} while (status_register.b7== 0) ;
NO
Erase Complete
if (status_register.b6==0) /*erase completed */ { writeToFlash (any_address, 0xFF) ;
read_data ( ) ; /*read data from another block*/ /*The device returns to Read Array (as if program/erase suspend was not issued).*/
Read data from another block or Program/Protection Program or Block Protect/Unprotect/Lock else
} { writeToFlash (any_address, 0xFF) ; read_program_data ( ); /*read or program data from another address*/ writeToFlash (any_address, 0xD0) ; /*write 0xD0 to resume erase*/ } }
Write D0h
Write FFh
Erase Continues
Read Data
AI90018b
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Figure 24. Locking Operations Flowchart and Pseudo Code
Start
Write 60h
locking_operation_command (address, lock_operation) { writeToFlash (any_address, 0x60) ; /*configuration setup*/ if (lock_operation==LOCK) /*to protect the block*/ writeToFlash (address, 0x01) ; else if (lock_operation==UNLOCK) /*to unprotect the block*/ writeToFlash (address, 0xD0) ; else if (lock_operation==LOCK-DOWN) /*to lock the block*/ writeToFlash (address, 0x2F) ; writeToFlash (any_address, 0x90) ;
Write 01h, D0h or 2Fh
Write 90h
Read Block Lock States
Locking change confirmed? YES Write FFh
NO
if (readFlash (address) ! = locking_state_expected) error_handler () ; /*Check the locking state (see Read Block Signature table )*/
writeToFlash (any_address, 0xFF) ; /*Reset to Read Array mode*/ }
End
AI05281
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M58CR032C, M58CR032D
Figure 25. Protection Register Program Flowchart and Pseudo Code
Start
Write C0h
protection_register_program_command (addressToProgram, dataToProgram) {: writeToFlash (any_address, 0xC0) ;
Write Address & Data
writeToFlash (addressToProgram, dataToProgram) ; /*Memory enters read status state after the Program Command*/ do { status_register=readFlash (any_address) ; /* E or G must be toggled*/
Read Status Register
b7 = 1 YES b3 = 0 YES b4 = 0 YES b1 = 0 YES End
NO } while (status_register.b7== 0) ;
NO
VPP Invalid Error (1, 2)
if (status_register.b3==1) /*VPP invalid error */ error_handler ( ) ;
NO
Program Error (1, 2)
if (status_register.b4==1) /*program error */ error_handler ( ) ;
NO
Program to Protected Block Error (1, 2)
if (status_register.b1==1) /*program to protect block error */ error_handler ( ) ;
}
AI05282
Note: 1. Status check of b1 (Protected Block), b3 (V PP Invalid) and b4 (Program Error) can be made after each program operation or after a sequence. 2. If an error is found, the Status Register must be cleared before further Program/Erase Controller operations.
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M58CR032C, M58CR032D
APPENDIX C. COMMAND INTERFACE STATE TABLES Table 36. Command Interface States - Lock table
Current State of the Current Bank Current State of Other Bank Command Input to the Current Bank (and Next State of the Current Bank) Erase Confirm P/E Resume Unlock Confirm (D0h) Block Lock Clear Read Unlock Block lock Read Status Electronic Lock-Down Confirm CFI Query Register Signature setup (01h) (98h) (50h) (90h) Set BCR setup (60h) Block LockDown Confirm (2Fh)
Mode
State
Others
Read Array (FFH)
Read Status Register (70h)
Set BCR Confirm (03h)
Any State
Read
Array CFI Electronic Signature Status
SEE Read MODIFY Read Array Read Array Status Read Array TABLE Register Block Lock Unlock Lock-Down Error, Set BCR Error Block lock Block Lock Unlock Unlock Lock-Down Lock-Down Error, Set Block BCR Error Block Lock Unlock Lock-Down Error, Set BCR Error Block Lock Unlock Lock-Down Error, Set BCR Error
Read Elect. Sign. Block Lock Unlock Lock-Down Error, Set BCR Error
Block Lock, Unlock, Read CFI Lock-Down, Read Array Read Array Read Array Set BCR Setup Block Lock Unlock Lock-Down Error, Set BCR Error Block Lock Block Lock Block Lock Unlock Unlock Unlock Lock-Down Set BCR Lock-Down Lock-Down Error, Set Block Block BCR Error
Setup Lock Unlock Lock-Down BCR
Any State
Error Lock SEE Read Unlock MODIFY Read Array Read Array Status Read Array Lock-Down TABLE Register Block Set BCR SEE Read MODIFY Read Array Read Array Status Read Array TABLE Register
Read Elect. Sign.
Block LocK Unlock Read CFI Lock-Down Read Array Read Array Read Array Setup, Set BCR Setup Block LocK Unlock Read CFI Lock-Down Read Array Read Array Read Array Setup, Set BCR Setup Block LocK Unlock Read CFI Lock-Down Read Array Read Array Read Array Setup, Set BCR Setup PS Read CFI Erase Error PS Read Array PS Read Array Erase Error PS Read Array Erase Error PS Read Array Erase Error
Protection Any State Register
Done
Read Elect. Sign.
Any State
ProgramDouble/ Quadruple Program
Done
SEE Read MODIFY Read Array Read Array Status Read Array TABLE Register
Read Elect. Sign.
Setup Idle Erase Suspend Idle
Read Array, CFI, Program Elect. Suspend Sign., Status Setup Block/ Bank Erase Error Done
SEE MODIFY TABLE Erase Error
PS Read Array Erase Error
Program (Busy) Erase (Busy)
PS Read Status Register Erase Error
PS Read Array Erase Error
PS Read Elect. Sign. Erase Error Read Elect. Sign.
Erase Error
Any State
SEE Read MODIFY Read Array Read Array Status Read Array TABLE Register Erase (Busy) ES Read Array Erase (Busy) ES Read Array
Block LocK Unlock Read CFI Lock-Down Read Array Read Array Read Array Setup, Set BCR Setup
Setup Busy Idle Program Suspend Erase Suspend Read Array, CFI, Elect. Sign., Status SEE MODIFY TABLE ES Read Array
ES Read Status Register
ES Read Array
ES Read Elect. Sign.
ES Read CFI
Block LocK Unlock ES Read Lock-Down Array Setup, Set BCR Setup
ES Read Array
ES Read Array
Note: PS = Program Suspend, ES = Erase Suspend.
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Table 37. Command Interface States - Modify Table
Current State of the Other Bank Setup Busy Idle Erase Suspend Program Suspend Setup Busy Idle Erase Suspend Program Suspend Idle Setup Busy Idle Erase Suspend Program Suspend Any State Idle Setup Busy Idle Erase Suspend Program Suspend Setup Idle Erase Suspend Program Double/ Quadruple Word Program Lock Unlock Lock-Down BCR Read Current State of the Current Bank Mode State Others Command Input to the Current Bank (and Next State of the Current Bank) Program Setup (10h/40h) Read Array Array, CFI, Electronic Signature, Status Register SEE LOCK TABLE Program setup Read Array Read Array Error, Lock Unlock Lock-Down Block, Set BCR Setup Busy Protection Register SEE LOCK TABLE Block Erase Setup (20h) Read Array Block Erase Setup Read Array Read Array Double/ Protection Quadruple Program-Erase Register Suspend (B0h) Program Setup Program Setup (30h/55h) (C0h) Read Array Protection Register Setup Read Array Read Array Double/ Quadruple Program Setup Read Array Read Array Double/ Quadruple Program Setup Read Array Bank Erase Setup (80h) Read Array Bank Erase Setup Read Array
Read Array Block Erase Setup Read Array Read Array
Read Array Protection Register Setup Read Array
Read Array Bank Erase Setup Read Array
Program setup Read Array
Protection Protection Protection Protection Protection Protection Protection Register (Busy) Register (Busy) Register (Busy) Register (Busy) Register (Busy) Register (Busy) Register (Busy) Read Array Read Array Block Erase Setup Read Array Read Array Protection Register Setup Read Array Read Array Double/ Quadruple Program Setup Read Array Read Array Bank Erase Setup Read Array
Done
SEE LOCK TABLE
Program Setup Read Array
Read Array
Setup Busy
Program (Busy) Program (Busy) Program (Busy) Program (Busy) PS Read Status Program (Busy) Program (Busy) Program (Busy) Register Read Array Read Array Block Erase Setup Read Array Read Array Read Array Protection Register Setup Read Array Read Array Double/ Quadruple Program Setup Read Array Read Array Bank Erase Setup Read Array
Done
SEE LOCK TABLE
Program Setup Read Array
Program Suspend
Read Array, CFI, Elect. Sign., Status Register Setup Busy
SEE LOCK TABLE SEE LOCK TABLE Erase (Busy)
PS Read Array PS Read Array PS Read Array PS Read Array PS Read Array PS Read Array
Idle Setup Busy Idle Program Suspend
Block/ Bank Erase
Erase Error Erase (Busy) ES Read Array
Erase Error Erase (Busy)
Erase Error ES Read Status Register
Erase Error Erase (Busy)
Erase Error Erase (Busy) ES Read Array
Erase Error Erase (Busy)
Erase Suspend
Read Array, CFI, Elect. Sign., Status Register
SEE LOCK TABLE
Program Setup ES Read Array ES Read Array ES Read Array ES Read Array
Double/ ES Read Array Quadruple Program Setup ES Read Array
Note: PS = Program Suspend, ES = Erase Suspend.
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Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are subject to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not authorized for use as critical components in life support devices or systems without express written approval of STMicroelectronics. The ST logo is registered trademark of STMicroelectronics All other names are the property of their respective owners. (c) 2002 STMicroelectronics - All Rights Reserved STMicroelectronics GROUP OF COMPANIES Australia - Brazil - Canada - China - Finland - France - Germany - Hong Kong - India - Israel - Italy - Japan - Malaysia - Malta Morocco - Singapore - Spain - Sweden - Switzerland - United Kingdom - United States www.st.com
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